'Timing Closure by Design,' a high frequency microprocessor design methodology Conference Paper uri icon


  • This paper presents a design methodology emphasizing early and quick timing closure for high frequency microprocessor designs. This methodology was used to design a Gigahertz class PowerPC microprocessor with 19 million transistors. Characteristics of 'Timing Closure by Design' are 1) logic partitioned on timing boundaries, 2) predictable control structures (PLAs), 3) static interfaces for dynamic circuits, 4) low skew clock distribution, 5) deterministic method of macro placement, 6) simplified timing analysis, and 7) refinement method of chip integration with early timing analysis.

published proceedings

  • Proceedings - Design Automation Conference

author list (cited authors)

  • Posluszny, S., Aoki, N., Boerstler, D., Coulman, P., Dhong, S., Flachs, B., ... et al.

complete list of authors

  • Posluszny, S||Aoki, N||Boerstler, D||Coulman, P||Dhong, S||Flachs, B||Hofstee, P||Kojima, N||Kwon, O||Lee, K||Meltzer, D||Nowka, K||Park, J||Peter, J||Silberman, J

publication date

  • January 2000