Multi-scenario buffer insertion in multi-core processor designs Conference Paper uri icon


  • Recently, microprocessor industry is headed in the direction of multi-core designs in order to continue the chip performance growth. We investigate buffer insertion, which is a critical timing optimization technique, in the context of an industrial multi-core processor design methodology. Different from the conventional formulation, buffer insertion in this case requires a single solution to accommodate different scenarios. If the conventional buffer insertion is performed for each scenario separately, there may be different solutions corresponding to these scenarios. A naive approach is to select one scenario's solution that is most critical among all scenarios and apply it to all the scenarios. However, a good solution for one scenario may be a poor one for another scenario. We propose algorithmic techniques for solving these multi-scenario buffer insertion problems. Compared to the naive approach, our algorithm can improve slack by 102ps on average for max-slack solutions. For min-cost solutions, our algorithm causes no timing violation while the naive approach results in 35% timing violations. Moreover, the computation speed of our algorithm is faster. Copyright 2008 ACM.

name of conference

  • the 2008 international symposium

published proceedings

  • Proceedings of the 2008 international symposium on Physical design - ISPD '08

author list (cited authors)

  • Liu, Y., Hu, J., & Shi, W.

citation count

  • 2

complete list of authors

  • Liu, Yifang||Hu, Jiang||Shi, Weiping

publication date

  • January 2008