Harvest rate of reconfigurable pipelines Academic Article

abstract

• For a reconfigurable architecture, the harvest rate is the expected percentage of defect-free processors that can be connected into the desired topology. In this paper, we give an analytical estimation for the harvest rate of reconfigurable multipipelines based on the following model: There are n pipelines each with m stages, where each stage of a pipeline is defective with identical independent probability 0.5 and spare wires are provided for reconfiguration. By formulating the "shifting" reconfiguration as weighted chains in a partial ordered set, we prove when n = (m), the harvest rate is between 34% and 72%. 1996 IEEE.

authors

• Shi, Weiping

published proceedings

• IEEE Transactions on Computers

author list (cited authors)

• Shi, W., Chang, M., & Fuchs, W. K.

citation count

• 2

complete list of authors

• Shi, Weiping||Chang, Ming-Feng||Fuchs, WK

publication date

• December 1996

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Computers  Journal

keywords

• 40 Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/12.543713

start page

• 1200

end page

• 1203

volume

• 45

issue

• 10

URL

• http://dx.doi.org/10.1109/12.543713