publication venue for
- A Voting Approach for Adaptive Network-on-Chip Power-Gating. 70:1962-1975. 2021
- Remote Control: A Simple Deadlock Avoidance Scheme for Modular Systems-on-Chip. 70:1928-1941. 2021
- Hardware Acceleration of Hash Operations in Modern Microprocessors. 70:1412-1426. 2021
- Revisiting the Optimization of Cauchy Reed-Solomon Coding Matrix for Fault-Tolerant Data Storage. 71:1839-1846. 2021
- Distributed Training of Support Vector Machine on a Multiple-FPGA System. 69:1015-1026. 2020
- FTCAM: An Area-Efficient Flash-Based Ternary CAM Design. 65:2652-2658. 2016
- A Hybrid Multicast Routing for Large Scale Sensor Networks with Holes. 64:3362-3375. 2015
- Adaptive-Acceleration Data Center TCP. 64:1522-1533. 2015
- Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. 64:733-746. 2015
- Fault Analysis-Based Logic Encryption. 64:410-424. 2015
- On the Minimum Link-Length Rectilinear Spanning Path Problem: Complexity and Algorithms. 63:3092-3100. 2014
- Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. 63:543-556. 2014
- An Energy-Efficient Memristive Threshold Logic Circuit. 61:474-487. 2012
- A Power and Throughput-Efficient Packet Classifier with n Bloom Filters. 60:1182-1193. 2011
- Localization Attacks to Internet Threat Monitors: Modeling and Countermeasures. 59:1655-1668. 2010
- A General Framework for Parameterized Schedulability Bound Analysis of Real-Time Systems. 59:776-783. 2010
- Design and Analysis of On-Chip Networks for Large-Scale Cache Systems. 59:332-344. 2010
- A Dynamic Slack Management Technique for Real-Time Distributed Embedded Systems. 57:215-230. 2008
- A holistic approach to designing energy-efficient cluster interconnects. 54:660-671. 2005
- EaseCAM: an energy and storage efficient TCAM-based router architecture for IP lookup. 54:521-533. 2005
- Locally subcube-connected hypercube networks: Theoretical analysis and experimental results. 51:530-540. 2002
- I-DDQ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays. 47:1136-1152. 1998
- Crash resilient communication in dynamic networks. 46:14-26. 1997
- Optimal parallel routing in star networks. 46:1293-1303. 1997
- A gate-level simulation environment for alpha-particle-induced transient faults. 45:1248-1256. 1996
- Harvest rate of reconfigurable pipelines. 45:1200-1203. 1996
- EFFICIENT IMPLEMENTATION TECHNIQUES FOR GRACEFULLY DEGRADABLE MULTIPROCESSOR SYSTEMS. 44:503-517. 1995
- NEW SELF-ROUTING PERMUTATION NETWORKS. 43:1319-1323. 1994
- A NEW CLASS OF OPTIMAL BOUNDED-DEGREE VLSI SORTING NETWORKS. 42:746-752. 1993
- AN ITERATION PARTITION APPROACH FOR CACHE OR LOCAL MEMORY THRASHING ON PARALLEL-PROCESSING. 42:529-546. 1993
- A FAST DISTRIBUTED SHORTEST-PATH ALGORITHM FOR A CLASS OF HIERARCHICALLY CLUSTERED DATA-NETWORKS. 41:710-724. 1992
- A NOVEL DIVISION ALGORITHM FOR THE RESIDUE NUMBER SYSTEM. 41:1026-1032. 1992
- A RAM ARCHITECTURE FOR CONCURRENT ACCESS AND ON-CHIP TESTING. 40:1153-1159. 1991
- OPTIMAL VLSI SORTING WITH REDUCED NUMBER OF PROCESSORS. 40:105-110. 1991
- ALGORITHM-BASED FAULT-DETECTION FOR SIGNAL-PROCESSING APPLICATIONS. 39:1304-1308. 1990
- Polynomial testing of packet switching networks. 38:202-217. 1989
- AN EVALUATION OF MULTIPLE-DISK I/O SYSTEMS. 38:1680-1690. 1989
- An Implementation of Mixed-Radix Conversion for Residue Number Applications. C-35:762-764. 1986
- A cost-effective multistage interconnection network with network overlapping and memory interleaving. C-34:1088-1101. 1985
- PAIRWISE REDUCTION FOR THE DIRECT, PARALLEL SOLUTION OF SPARSE, UNSYMMETRIC SETS OF LINEAR-EQUATIONS. 37:1648-1654.