A robust, fast pulsed flip-flop design Conference Paper uri icon

abstract

  • High Speed VLSI design utilizes heavy pipelining, resulting in a large number of flip-flops in the circuit. Hence there is a strong motivation to design fast, low power and area efficient flip-flops. In this paper, we present a pulsed flip-flop design based on a novel pulse generator circuit. Our design achieves significantly improved speed when compared to recent pulsed flip-flop design, as well as a traditional masterslave D flip-flop. Monte Carlo simulations demonstrate that our design is significantly more robust to variations than the other flip-flops. Our design consumes low power as well. Also we have performed the layout of our design and shown that our layout area is smaller than a traditional D flip-flop. Copyright 2008 ACM.

name of conference

  • Proceedings of the 18th ACM Great Lakes symposium on VLSI

published proceedings

  • Proceedings of the 18th ACM Great Lakes symposium on VLSI

author list (cited authors)

  • Venkatraman, A., Garg, R., & Khatri, S. P.

citation count

  • 9

complete list of authors

  • Venkatraman, Arunprasad||Garg, Rajesh||Khatri, Sunil P

publication date

  • January 2008