An Efficient and Regular Routing Methodology for Datapath Designs Using Net Regularity Extraction Academic Article uri icon


  • We present a new detailed routing methodology specifically designed for datapath layouts. In typical state-of-the-art microprocessor designs, datapaths comprise about 70% of the logic (excluding caches). However, most logic and layout synthesis research has targeted random-logic portions of the design. In general, techniques for random-logic placement and routing do not produce good results for datapath layouts. Although research on datapath placement and global routing has been reported, very little research has been reported in the area of detailed routing for datapaths. Our datapath routing methodology exploits the unique feature of datapaths, namely, their regularity. Datapaths typically comprise regular structures (or bit slices), which are replicated. The interconnections between these replicated bit slices are also typically very regular. Our datapath routing methodology utilizes new techniques to extract interconnect regularity among bit slices. We define a net cluster, which is collection of similarly structured nets present across different bit slices. We introduce two clustering schemes (footprint-driven clustering and instance-driven clustering) to extract such net clusters. Using these net clusters, we select one representative bit slice to perform a strap-based routing (which optimally finds the shortest path between two points if that path is available) on a member net of each net cluster. Then for each such net, we propagate its route to all other nets in its net cluster. Our algorithm is unique in that it performs the detailed routing on a single bit slice and infers the routing for all bit slices using the notion of net clusters. Since we only route a small fraction of nets present in the design, significant speedup is obtained. We demonstrate at least six times speedup for industrial 32-and 64-bit datapath designs. The regularity of the routes across the bit slices results in more predictable timing characteristics for the resulting layout.

published proceedings

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

altmetric score

  • 3

author list (cited authors)

  • Das, S., & Khatri, S. P.

citation count

  • 6

complete list of authors

  • Das, Sabyasachi||Khatri, Sunil P

publication date

  • January 2002