A timing-driven hybrid-compression algorithm for faster sum-of-products

In state-of-the-art Digital Signal Processing (DSP) and Graphics applications, the arithmetic Sum-of-Product (SOP) is an important and computationally intensive operation, consuming a significant amount of delay. This paper presents a new architectural optimization approach to synthesize a faster Sum-of-Product block, which can be very useful to reduce the delay in the critical path of the design. We have divided the problem of generating the Sum-of-Product (SOP) into three parts: creation of the BitClusters (sets of individual partial-product bits, which belong to the ith bitslice), hybrid compression-based reduction of the BitClusters and computation of the final sum result. Techniques used in all these three steps help to produce a faster implementation for the overall SOP block. Our experimental data shows that the SOP block generated by our algorithm is significantly faster (3.49% faster on average) than the corresponding block generated by a commercially available synthesis tool.

Proceedings of the Fifth IASTED International Conference on Circuits, Signals, and Systems, CSS 2007

A timing-driven hybrid-compression algorithm for faster sum-of-products Conference Paper