Practical Techniques to Reduce Skew and its Variations in Buffered Clock Networks**This work is supported in part by Semiconductor Research Corporation under contract number 2004-TJ-1205.
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Clock skew is becoming increasingly difficult to control due to variations. Link based non-tree clock distribution is a cost-effective technique for reducing clock skew variations. However, previous works based on this technique were limited to unbuffered clock networks and neglected spatial correlations in the experimental validation. In this work, we overcome these shortcomings and make the link based non-tree approach feasible for realistic designs. The short circuit risk and multi-driver delay issues in buffered non-tree clock networks are investigated. Our approach is validated with SPICE based Monte Carlo simulations, considering spatial correlations among variations. The experimental results show that our approach can reduce the maximal skew by 47%, improve the skew yield from 15% to 73% on average with a decrease on the total wire and buffer capacitance. © 2005 IEEE.
author list (cited authors)
Venkataraman, G., Javakumar, N., Hu, J., Li, P., Khatri, S., Rajaram, A., McGuinness, P., & Alpert, C.