A fast, source-synchronous ring-based network-on-chip design
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Most network-on-chip (NoC) architectures are based on a mesh-based interconnection structure. In this paper, we present a new NoC architecture, which relies on source synchronous data transfer over a ring. The source synchronous ring data is clocked by a resonant clock, which operates significantly faster than individual processors that are served by the ring. This allows us to significantly improve the cross section bandwidth and the latency of the NoC. We have validated the design using a 22nm predictive process. Compared to the state-of-the-art mesh based NoC, our scheme achieves a 4.5x better bandwidth, 7.4x better contention free latency with 11% lower area and 35% lower power. 2012 EDAA.
name of conference
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE 2012)
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)
author list (cited authors)
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
complete list of authors
Mandal, A||Khatri, SP||Mahapatra, RN