Techniques to Improve the Efficiency of SAT based Path Delay Test Generation Conference Paper

abstract

• Boolean Satisfiability (SAT) solvers have been used to speed up test pattern generation. In this work, several techniques to speed up SAT-based path delay test generation are presented. We demonstrate that these techniques: circuit simplification, Dynamic SAT Solving, Circuit Observability Don't Cares and Approximate Observability Don't Cares, significantly improve the efficiency of path delay test generation. The effectiveness of these techniques has been demonstrated on benchmark and industrial designs. 2014 IEEE.

name of conference

• 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems

authors

• Khatri, Sunil
• Walker, Duncan

published proceedings

• 2014 27TH INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2014 13TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID 2014)

author list (cited authors)

• Bian, K., Walker, D., & Khatri, S. P.

citation count

• 1

complete list of authors

• Bian, Kun||Walker, DMH||Khatri, Sunil P

publication date

• January 2014

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the IEEE International Conference on VLSI Design  Journal

keywords

• Observability
• Path Delay Test
• Satisfiability

Digital Object Identifier (DOI)

• 10.1109/VLSID.2014.16

International Standard Book Number (ISBN) 13

• 9781479925124

start page

• 50

end page

• 55

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fvlsid.2014.16