Mixed Structural-Functional Path Delay Test Generation and Compaction Conference Paper

abstract

• This work considers the use of a mixed structural-functional approach to path delay fault test generation and compaction. K Longest Paths per Gate (KLPG) are generated using structural information and filtered using direct implications and heuristics. These paths are then justified using Boolean satisfiability (SAT) algorithms. The paths are dynamically compacted into test patterns, using structural information to identify most conflicts, before final checking with SAT. Advanced SAT algorithms based on structural information of the circuit are investigated to improve SAT performance. Compared to structural-only approaches, the combined structural-functional approach achieves a better test compaction ratio in less CPU time on benchmark circuits. The improvement is more apparent when generatingpseudo functional KLPG tests. 2013 IEEE.

name of conference

• 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

authors

• Khatri, Sunil
• Walker, Duncan

published proceedings

• PROCEEDINGS OF THE 2013 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS)

author list (cited authors)

• Bian, K., Walker, D., Khatri, S. P., & Lahiri, S.

citation count

• 8

complete list of authors

• Bian, Kun||Walker, DMH||Khatri, Sunil P||Lahiri, Shayak

publication date

• October 2013

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/dft.2013.6653575

International Standard Book Number (ISBN) 13

• 978-1-4799-1583-5

start page

• 7

end page

• 12

URL

• http://dx.doi.org/10.1109/dft.2013.6653575