Sneak-path Testing of Memristor-based Memories Conference Paper

abstract

• Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by 32%. 2013 IEEE.

name of conference

• 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems

authors

• Rajendran, Jeyavijayan

published proceedings

• 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems

author list (cited authors)

• Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O.

citation count

• 36

complete list of authors

• Kannan, Sachhidh||Rajendran, Jeyavijayan||Karri, Ramesh||Sinanoglu, Ozgur

publication date

• January 2013

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the IEEE International Conference on VLSI Design  Journal

Digital Object Identifier (DOI)

• 10.1109/vlsid.2013.219

International Standard Book Number (ISBN) 13

• 9780769548890

start page

• 386

end page

• 391

URL

• http://dx.doi.org/10.1109/vlsid.2013.219