HR job title
- Assistant Professor
- Contact Info
Rajendran, Jeyavijayan Associate Professor - Term Appoint
Positions
- Associate Professor - Term Appoint, Electrical and Computer Engineering, College of Engineering
- Overview
- Publications
- Research
- Teaching
- Background
- Contact
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Overview
Publications
selected publications
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academic article
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Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2020).
Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Transactions on Emerging Topics in Computing.
8(2), 517-532.
-
Wang, Y., Chen, P. u., Hu, J., Li, G., & Rajendran, J.
(2018).
The Cat and Mouse in Split Manufacturing. IEEE Transactions on Very Large Scale Integration Systems.
26(5), 805-817.
-
Yasin, M., Sinanoglu, O., & Rajendran, J.
(2017).
Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. IEEE Transactions on Information Forensics and Security.
12(11), 2668-2682.
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Rajendran, J., Sinanoglu, O., & Karri, R.
(2016).
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. IEEE Transactions on Very Large Scale Integration Systems.
24(9), 2946-2959.
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Yasin, M., Rajendran, J., Sinanoglu, O., & Karri, R.
(2016).
On Improving the Security of Logic Locking. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
35(9), 1411-1424.
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Ali, S. S., Ibrahim, M., Rajendran, J., Sinanoglu, O., & Chakrabarty, K.
(2016).
Supply-Chain Security of Digital Microfluidic Biochips. Computer.
49(8), 36-43.
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Zeltmann, S. E., Gupta, N., Tsoutsos, N. G., Maniatakos, M., Rajendran, J., & Karri, R.
(2016).
Manufacturing and Security Challenges in 3D Printing. Journal of Metals.
68(7), 1872-1881.
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Rajendran, J., Ali, A., Sinanoglu, O., & Karri, R.
(2015).
Belling the CAD: Toward Security-Centric Electronic System Design. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
34(11), 1756-1769.
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Rajendran, J., Karri, R., Wendt, J. B., Potkonjak, M., McDonald, N., Rose, G. S., & Wysocki, B.
(2015).
Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications. Proceedings of the Institute of Electrical and Electronics Engineers (IEEE).
103(5), 829-849.
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Rajendran, J., Karri, R., & Rose, G. S.
(2015).
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. IEEE Transactions on Computers.
64(3), 733-746.
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Rajendran, J., Zhang, H., Zhang, C., Rose, G. S., Pino, Y., Sinanoglu, O., & Karri, R.
(2015).
Fault Analysis-Based Logic Encryption. IEEE Transactions on Computers.
64(2), 410-424.
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Liu, C., Rajendran, J., Yang, C., & Karri, R.
(2014).
Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling. IEEE Transactions on Emerging Topics in Computing.
2(4), 461-472.
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Rajendran, J., Sinanoglu, O., & Karri, R.
(2014).
Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proceedings of the Institute of Electrical and Electronics Engineers (IEEE).
102(8), 1266-1282.
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Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O.
(2013).
Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories. IEEE Transactions On Nanotechnology.
12(3), 413-426.
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Rajendran, J., Kanuparthi, A. K., Zahran, M., Addepalli, S. K., Ormazabal, G., & Karri, R.
(2013).
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. IEEE Design & Test.
30(2), 35-44.
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Rose, G. S., Rajendran, J., Manem, H., Karri, R., & Pino, R. E.
(2012).
Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Proceedings of the Institute of Electrical and Electronics Engineers (IEEE).
100(6), 2033-2049.
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Manem, H., Rajendran, J., & Rose, G. S.
(2012).
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. IEEE Transactions on Circuits and Systems I: Regular Papers.
59(5), 1051-1060.
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Rajendran, J., Manem, H., Karri, R., & Rose, G. S.
(2012).
An Energy-Efficient Memristive Threshold Logic Circuit. IEEE Transactions on Computers.
61(4), 474-487.
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Manem, H., Rajendran, J., & Rose, G. S.
(2012).
Design Considerations for Multilevel CMOS/Nano Memristive Memory. ACM Journal on Emerging Technologies in Computing Systems.
8(1), 1-22.
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Tehranipoor, M., Salmani, H., Zhang, X., Wang, M., Karri, R., Rajendran, J., & Rosenfeld, K.
(2011).
Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges. Computer.
44(7), 66-74.
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Karri, R., Rajendran, J., Rosenfeld, K., & Tehranipoor, M.
(2010).
Trustworthy Hardware: Identifying and Classifying Hardware Trojans. Computer.
43(10), 39-46.
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Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2020).
Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Transactions on Emerging Topics in Computing.
8(2), 517-532.
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chapter
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Jyothi, V., & Rajendran, J.
(2018).
Hardware Trojan Attacks in FPGA and Protection Approaches. The Hardware Trojan War.
(pp. 345-368).
Springer International Publishing.
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Rajendran, J., & Garg, S.
(2017).
Logic Encryption. Hardware Protection through Obfuscation.
(pp. 71-88).
Springer International Publishing.
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Karri, R., Sinanoglu, O., & Rajendran, J.
(2017).
Physical Unclonable Functions and Intellectual Property Protection Techniques. Fundamentals of IP and SoC Security.
(pp. 199-222).
Springer International Publishing.
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Garg, S., & Rajendran, J.
(2017).
Split Manufacturing. Hardware Protection through Obfuscation.
(pp. 243-262).
Springer International Publishing.
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Karri, R., Rajendran, J., & Rosenfeld, K.
(2012).
Trojan Taxonomy. Introduction to Hardware Security and Trust.
(pp. 325-338).
Springer New York.
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Jyothi, V., & Rajendran, J.
(2018).
Hardware Trojan Attacks in FPGA and Protection Approaches. The Hardware Trojan War.
(pp. 345-368).
Springer International Publishing.
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conference paper
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(2019).
Layout recognition attacks on split manufacturing. 45-50.
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(2018).
Towards provably-secure analog and mixed-signal locking against overproduction. 2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD).
1-8.
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Commarota, R. o., Karimi, N., Garg, S., & Rajendran, J.
(2018).
Special session: Recent developments in hardware security. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
1-1.
-
(2018).
Towards provably-secure performance locking. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1592-1597.
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Di Crescenzo, G., Rajendran, J., Karri, R., & Memon, N.
(2017).
Boolean Circuit Camouflage. 7-16.
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Wang, Y., Cao, T., Hu, J., & Rajendran, J.
(2017).
Front-end-of-line attacks in split manufacturing. 2007 IEEE/ACM International Conference on Computer-Aided Design.
1-8.
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Feng, L., Wang, Y., Hu, J., Mak, W., & Rajendran, J
(2017).
Making split fabrication synergistically secure and manufacturable. 2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD).
321-328.
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Feng, L., Wang, Y., Hu, J., Mak, W., & Rajendran, J
(2017).
Making split fabrication synergistically secure and manufacturable. 2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD).
313-320.
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Alagappan, M., Rajendran, J., Doroslovacki, M., & Venkataramani, G.
(2017).
DFS covert channels on multi-core platforms. 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).
1-6.
-
(2017).
Provably-Secure Logic Locking. 1601-1618.
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Yasin, M., Sengupta, A., Nabeel, M. T., Ashraf, M., Rajendran, J., & Sinanoglu, O.
(2017).
Provably-Secure logic locking: From theory to practice. Proceedings of the ACM Conference on Computer and Communications Security.
1601-1618.
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Rajendran, J.
(2017).
An overview of hardware intellectual property protection. 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
1-4.
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Broadfoot, T., Sechen, C., & Rajendran, J.
(2017).
On designing optimal camouflaged layouts. 169-169.
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Yasin, M., Mazumdar, B., Rajendran, J., & Sinanoglu, O.
(2017).
TTLock: Tenacious and traceless logic locking. 166-166.
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Yasin, M., Sengupta, A., Schafer, B. C., Makris, Y., Sinanoglu, O., & Rajendran, J.
(2017).
What to Lock?. 351-356.
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Wang, Y., Chen, P. u., Hu, J., & Rajendran, J
(2017).
Routing perturbation for enhanced security in split manufacturing. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
605-610.
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Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2017).
Security analysis of Anti-SAT. 342-347.
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Majumder, M. B., Uddin, M., Rose, G. S., & Rajendran, J.
(2016).
Sneak path enabled authentication for memristive crossbar memories. 1-6.
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Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2016).
CamoPerturb. 2007 IEEE/ACM International Conference on Computer-Aided Design.
1-8.
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Yang, C., Liu, B., Li, H., Chen, Y., Wen, W., Barnell, M., Wu, Q., & Rajendran, J.
(2016).
Security of neuromorphic computing. 2007 IEEE/ACM International Conference on Computer-Aided Design.
1-6.
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Bidmeshki, M., Reddy, G. R., Zhou, L., Rajendran, J., & Makris, Y.
(2016).
Hardware-based attacks to compromise the cryptographic security of an election system. 153-156.
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Wang, Y., Chen, P. u., Hu, J., & Rajendran, J
(2016).
The cat and mouse in split manufacturing. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
1-6.
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Kanuparthi, A., Rajendran, J., & Karri, R.
(2016).
Controlling your control flow graph. 43-48.
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Yasin, M., Mazumdar, B., Rajendran, J., & Sinanoglu, O.
(2016).
SARLock: SAT attack resistant logic locking. 236-241.
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Tang, J., Karri, R., & Rajendran, J.
(2016).
Securing pressure measurements using SensorPUFs. 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
1330-1333.
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Yasin, M., Saeed, S. M., Rajendran, J., & Sinanoglu, O.
(2016).
Activation of logic encrypted chips: Pre-test or post-test?. 139-144.
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Rajendran, J., Dhandayuthapany, A. M., Vedula, V., & Karri, R.
(2016).
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
547-552.
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Rajendran, J., Vedula, V., & Karri, R.
(2015).
Detecting malicious modifications of data in third-party intellectual property cores. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
1-6.
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Shahrjerdi, D., Rajendran, J., Garg, S., Koushanfar, F., & Karri, R.
(2014).
Shielding and securing integrated circuits with sensors. 2007 IEEE/ACM International Conference on Computer-Aided Design.
170-174.
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Hoe, D., Rajendran, J., & Karri, R.
(2014).
Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors. 2009 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI.
516-521.
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Natarajan, S., Majumdar, A., & Rajendran, J.
(2014).
Hot topic session 9C: Test and fault tolerance for emerging memory technologies. 1-1.
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Waksman, A., Rajendran, J., Suozzo, M., & Sethumadhavan, S.
(2014).
A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
1-4.
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Rostami, M., Koushanfar, F., Rajendran, J., & Karri, R.
(2013).
Hardware security: Threat models and metrics. 2007 IEEE/ACM International Conference on Computer-Aided Design.
819-823.
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Liu, C., Rajendran, J., Yang, C., & Karri, R.
(2013).
Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
101-106.
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Rajendran, J., Sinanoglu, O., & Karri, R.
(2013).
VLSI testing based security metric for IC camouflaging. 2013 IEEE International Test Conference (ITC).
1-4.
-
Rajendran, J., Huan Zhang, .., Sinanoglu, O., & Karri, R.
(2013).
High-level synthesis for security and trust. 232-233.
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Sinanoglu, O., Karimi, N., Rajendran, J., Karri, R., Jin, Y., Huang, K., & Makris, Y.
(2013).
Reconciling the IC test and security dichotomy. 1-6.
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Zhang, X., Xiao, K., Tehranipoor, M., Rajendran, J., & Karri, R.
(2013).
A study on the effectiveness of Trojan detection techniques using a red team blue team approach. 1-3.
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Rose, G. S., Rajendran, J., McDonald, N., Karri, R., Potkonjak, M., & Wysocki, B.
(2013).
Hardware security strategies exploiting nanoelectronic circuits. 368-372.
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Rajendran, J., Sinanoglu, O., & Karri, R.
(2013).
Is Split Manufacturing Secure?. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1259-1264.
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Rajendran, J., Sam, M., Sinanoglu, O., & Karri, R.
(2013).
Security analysis of integrated circuit camouflaging. Proceedings of the ACM Conference on Computer and Communications Security.
709-720.
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Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O.
(2013).
Sneak-path Testing of Memristor-based Memories. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
386-391.
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Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O.
(2012).
Engineering crossbar based emerging memory technologies. 2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS.
478-479.
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Rajendran, J., Rose, G. S., Karri, R., & Potkonjak, M.
(2012).
Nano-PPUF: A Memristor-Based Security Primitive. 84-87.
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Rajendran, J., Pino, Y., Sinanoglu, O., & Karri, R.
(2012).
Security analysis of logic obfuscation. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
83-89.
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Rajendran, J., Pino, Y., Sinanoglu, O., & Karri, R.
(2012).
Logic encryption: A fault analysis perspective. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
953-958.
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Rajendran, J., Jyothi, V., & Karri, R.
(2011).
Blue team red team approach to hardware trust assessment. 2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS.
285-288.
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Rajendran, J., Jyothi, V., Sinanoglu, O., & Karri, R.
(2011).
Design and analysis of ring oscillator based Design-for-Trust technique. 105-110.
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Rajendran, J., Karri, R., & Rose, G. S.
(2011).
Parallel memristors: Improving variation tolerance in memristive digital circuits. 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
2241-2244.
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Rajendran, J., Maenm, H., Karri, R., & Rose, G. S.
(2011).
An Approach to Tolerate Process Related Variations in Memristor-Based Applications. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
18-23.
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Rajendran, J., Manem, H., Karri, R., & Rose, G. S.
(2010).
Memristor based programmable threshold logic array. 5-10.
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Rajendran, J., Borad, H., Mantravadi, S., & Karri, R.
(2010).
SLICED: Slide-based concurrent error detection technique for symmetric block ciphers. 70-75.
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Rajendran, J., Gavas, E., Jimenez, J., Padman, V., & Karri, R.
(2010).
Towards a comprehensive and systematic classification of hardware Trojans. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
1871-1874.
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Rajendran, J., Manem, H., & Rose, G. S.
(2009).
NDR based threshold logic fabric with memristive synapses. 725-728.
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Chandrasekaran, S., Rajendran, J., & Annamalai, A.
(2008).
Data driven security alarm model for embedded applications. 1-5.
-
(2019).
Layout recognition attacks on split manufacturing. 45-50.
Research
principal investigator on
- Collaborative Research: EAGER: SaTC-EDU: Dynamic Adaptive Machine Learning for Teaching Hardware Security (DYNAMITES) awarded by Directorate for Education & Human Resources - (Arlington, Virginia, United States) 2020 - 2022
- CAREER: Towards Provably-Secure Design of Integrated Circuits awarded by National Science Foundation - (Arlington, Virginia, United States) 2017 - 2022
- Towards verification-guided hardware synthesis for security awarded by United States Department of the Navy - (Arlington, Virginia, United States) 2018 - 2021
- EAGER: Collaborative: Secure and Trustworthy Cyberphysical Microfluidic Systems awarded by National Science Foundation - (Arlington, Virginia, United States) 2018 - 2020
- Secure System-on-Chip Challenge: A Red Team-Blue Team Stress Test for State-of-the-Art System-on-Chip Designs awarded by United States Army - (Washington D.C., District of Columbia, United States) 2018 - 2019
- STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs awarded by National Science Foundation - (Arlington, Virginia, United States) 2017 - 2019
co-principal investigator on
Teaching
teaching activities
- ECEN248 Intro To Dgtl Sym Dsgn Instructor
- ECEN426 Security Of Embedded Systems Instructor
- ECEN454 Dig Integratedckt Des Instructor
- ECEN489 Sptp: Security Embedded Sys Instructor
- ECEN489 Sptp:security Embedded Sys Instructor
- ECEN491 Hnr-research Instructor
- ECEN685 Directed Studies Instructor
- ECEN689 Sptp:harware Security Instructor
- ECEN691 Research Instructor
- ECEN714 Digital Integrated Circuit Des Instructor
- ECEN759 Hardware Security Instructor
Background
education and training
- Ph.D. in Electrical Engineering, New York University - (New York, New York, United States) 2015
- M.S. in Computer Engineering, New York University - (New York, New York, United States) 2011
- B.E. in Electronics and Communication Engineering, Anna University, Chennai - (Chennai, Tamil Nadu, India) 2008
awards and honors
Contact
first name
- Jeyavijayan
has last name
- Rajendran
mailing address
-
Texas A&M University
Electrical Engineering
3128 TAMU
College Station, TX 77843-3128
USA
Other
- jeyavijayan@tamu.edu