HR job title
- Associate Professor
- Contact Info
Rajendran, Jeyavijayan
Positions
- Assistant Professor, Electrical and Computer Engineering, College of Engineering
- Overview
- Publications
- Research
- Teaching
- Background
- Contact
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Overview
Publications
selected publications
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academicarticle
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Huang, P., Kim, J., Kumar, P. R., Rajendran, J., & Enjeti, P.
(2024).
Enhancing Cybersecurity for Industrial Control Systems: Innovations in Protecting PLC-Dependent Industrial Infrastructures. IEEE Internet of Things Journal.
PP(99), 1-1.
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Rostami, M., Chen, C., Kande, R., Li, H., Rajendran, J., & Sadeghi, A.
(2024).
Fuzzerfly Effect: Hardware Fuzzing for Memory Safety. IEEE Security and Privacy.
PP(99), 2-12.
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Han, Z., Dixit, A., Patnaik, S., & Rajendran, J.
(2024).
STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
PP(99), 1-1.
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Gohil, V., Patnaik, S., Guo, H., Kalathil, D., & Rajendran, J.
(2023).
DETERRENT: Detecting Trojans Using Reinforcement Learning. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
PP(99), 1-1.
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Devadas, S., & Rajendran, J.
(2022).
Guest Editors' Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security. IEEE Design and Test.
39(4), 5-6.
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Jayasankaran, N. G., Borbon, A. S., Sanchez-Sinencio, E., Hu, J., & Rajendran, J.
(2022).
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. IEEE Transactions on Emerging Topics in Computing.
10(1), 386-403.
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Garg, S., Holcomb, D., Rajendran, J., & Sadeghi, A.
(2021).
Guest Editors' Introduction: Competing to Secure SoCs. IEEE Design and Test.
38(1), 5-6.
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Sanabria-Borbon, A., Jayasankaran, N. G., Hu, J., Rajendran, J., & Sanchez-Sinencio, E.
(2021).
Analog/RF IP Protection: Attack Models, Defense Techniques, and Challenges. 68(1), 36-41.
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Gohil, V., Tressler, M., Sipple, K., Patnaik, S., & Rajendran, J.
(2021).
Games, Dollars, Splits: A Game-Theoretic Analysis of Split Manufacturing. IEEE Transactions on Information Forensics and Security.
16, 5077-5092.
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Jayasankaran, N. G., Sanabria-Borbon, A., Abuellil, A., Sanchez-Sinencio, E., Hu, J., & Rajendran, J.
(2020).
Breaking Analog Locking Techniques. 28(10), 2157-2170.
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Chakraborty, A., Jayasankaran, N. G., Liu, Y., Rajendran, J., Sinanoglu, O., Srivastava, A., ... Zuzak, M.
(2020).
Keynote: A Disquisition on Logic Locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
39(10), 1952-1972.
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Yang, C., Liu, B., Li, H., Chen, Y., Barnell, M., Wu, Q., Wen, W., & Rajendran, J.
(2020).
Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
39(10), 2192-2205.
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Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2020).
Removal Attacks on Logic Locking and Camouflaging Techniques. IEEE Transactions on Emerging Topics in Computing.
8(2), 517-532.
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Wang, Y., Chen, P. u., Hu, J., Li, G., & Rajendran, J.
(2018).
The Cat and Mouse in Split Manufacturing. IEEE Transactions on Very Large Scale Integration Systems.
26(5), 805-817.
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Yasin, M., Sinanoglu, O., & Rajendran, J.
(2017).
Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging. IEEE Transactions on Information Forensics and Security.
12(11), 2668-2682.
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Rajendran, J. J., Sinanoglu, O., & Karri, R.
(2016).
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. IEEE Transactions on Very Large Scale Integration Systems.
24(9), 2946-2959.
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Yasin, M., Rajendran, J. J., Sinanoglu, O., & Karri, R.
(2016).
On Improving the Security of Logic Locking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
35(9), 1411-1424.
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Zeltmann, S. E., Gupta, N., Tsoutsos, N. G., Maniatakos, M., Rajendran, J., & Karri, R.
(2016).
Manufacturing and Security Challenges in 3D Printing. JOM.
68(7), 1872-1881.
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Ali, S. S., Ibrahim, M., Rajendran, J., Sinanoglu, O., & Chakrabarty, K.
(2016).
Supply-Chain Security of Digital Microfluidic Biochips. Computer.
49(8), 36-43.
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Rajendran, J., Ali, A., Sinanoglu, O., & Karri, R.
(2015).
Belling the CAD: Toward Security-Centric Electronic System Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
34(11), 1756-1769.
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Rajendran, J., Karri, R., & Rose, G. S.
(2015).
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors. IEEE Transactions on Computers.
64(3), 733-746.
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Rajendran, J., Zhang, H., Zhang, C., Rose, G. S., Pino, Y., Sinanoglu, O., & Karri, R.
(2015).
Fault Analysis-Based Logic Encryption. IEEE Transactions on Computers.
64(2), 410-424.
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Rajendran, J., Karri, R., Wendt, J. B., Potkonjak, M., McDonald, N., Rose, G. S., & Wysocki, B.
(2015).
Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications. Proceedings of the IEEE.
103(5), 829-849.
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Liu, C., Rajendran, J., Yang, C., & Karri, R.
(2014).
Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling. IEEE Transactions on Emerging Topics in Computing.
2(4), 461-472.
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Rajendran, J., Sinanoglu, O., & Karri, R.
(2014).
Regaining Trust in VLSI Design: Design-for-Trust Techniques. Proceedings of the IEEE.
102(8), 1266-1282.
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Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O.
(2013).
Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories. IEEE Transactions On Nanotechnology.
12(3), 413-426.
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Rajendran, J., Kanuparthi, A. K., Karri, R., Addepalli, S. K., Zahran, M., & Ormazabal, G.
(2013).
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach. IEEE Design and Test.
30(2), 35-44.
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Rose, G. S., Rajendran, J., Manem, H., Karri, R., & Pino, R. E.
(2012).
Leveraging Memristive Systems in the Construction of Digital Logic Circuits. Proceedings of the IEEE.
100(6), 2033-2049.
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Manem, H., Rajendran, J., & Rose, G. S.
(2012).
Design Considerations for Multilevel CMOS/Nano Memristive Memory. ACM Journal on Emerging Technologies in Computing Systems.
8(1), 6-22.
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Rajendran, J., Manem, H., Karri, R., & Rose, G. S.
(2012).
An Energy-Efficient Memristive Threshold Logic Circuit. IEEE Transactions on Computers.
61(4), 474-487.
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Manem, H., Rajendran, J., & Rose, G. S.
(2012).
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array. 59(5), 1051-1060.
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Tehranipoor, M., Salmani, H., Zhang, X., Wang, X., Karri, R., Rajendran, J., & Rosenfeld, K.
(2011).
Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges. Computer.
44(7), 66-74.
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Karri, R., Rajendran, J., Rosenfeld, K., & Tehranipoor, M.
(2010).
Trustworthy Hardware: Identifying and Classifying Hardware Trojans. Computer.
43(10), 39-46.
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Huang, P., Kim, J., Kumar, P. R., Rajendran, J., & Enjeti, P.
(2024).
Enhancing Cybersecurity for Industrial Control Systems: Innovations in Protecting PLC-Dependent Industrial Infrastructures. IEEE Internet of Things Journal.
PP(99), 1-1.
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book
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Trustworthy Hardware Design: Combinational Logic Locking Techniques Preface. Springer Nature.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Trustworthy Hardware Design: Combinational Logic Locking Techniques Preface. Springer Nature.
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chapter
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Jayasankaran, N. G., Sanabria-Borbn, A., Snchez-Sinencio, E., Hu, J., & Rajendran, J.
(2021).
Analog IP Protection and Evaluation. Emerging Topics in Hardware Security.
(pp. 419-469).
Springer Nature.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Discussion. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 131-132).
Wolters Kluwer.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
A Brief History of Logic Locking. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 17-31).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Appendix A Background on VLSI Test. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 139-142).
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Approximate Attacks. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 69-76).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Post-SAT 1: Point Function-Based Logic Locking. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 57-67).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Post-SAT 2: Insertion of SAT-Unresolvable Structures. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 93-102).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Post-SAT 3: Stripped-Functionality Logic Locking. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 103-118).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Pre-SAT Logic Locking. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 33-46).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Side-Channel Attacks. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 119-130).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
Structural Attacks. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 77-92).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
The Need for Logic Locking. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 1-16).
Springer International Publishing.
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Yasin, M., Rajendran, J., & Sinanoglu, O.
(2020).
The SAT Attack. TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES.
(pp. 47-56).
Springer International Publishing.
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Yasin, M., Mazumdar, B., Rajendran, J., & Sinanoglu, O.
(2019).
Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution. The IoT Physical Layer.
(pp. 353-373).
Springer Nature.
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Jyothi, V., & Rajendran, J. J.
(2018).
Hardware Trojan Attacks in FPGA and Protection Approaches. The Hardware Trojan War.
(pp. 345-368).
Springer Nature.
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Rajendran, J. J., & Garg, S.
(2017).
Logic Encryption. Hardware Protection through Obfuscation.
(pp. 71-88).
Springer Nature.
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Karri, R., Sinanoglu, O., & Rajendran, J.
(2017).
Physical Unclonable Functions and Intellectual Property Protection Techniques. Fundamentals of IP and SoC Security.
(pp. 199-222).
Springer Nature.
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Garg, S., & Rajendran, J. J.
(2017).
Split Manufacturing. Hardware Protection through Obfuscation.
(pp. 243-262).
Springer Nature.
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Karri, R., Rajendran, J., & Rosenfeld, K.
(2012).
Trojan Taxonomy. Introduction to Hardware Security and Trust.
(pp. 325-338).
Springer Nature.
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Jayasankaran, N. G., Sanabria-Borbn, A., Snchez-Sinencio, E., Hu, J., & Rajendran, J.
(2021).
Analog IP Protection and Evaluation. Emerging Topics in Hardware Security.
(pp. 419-469).
Springer Nature.
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conference paper
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Gohil, V., Guo, H., Patnaik, S., & Rajendran, J.
(2022).
ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. 1275-1289.
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Bhunia, S., Das, A., Fazzari, S., Kammler, V., Kehlet, D., Rajendran, J., & Srivastava, A.
(2022).
Hardware IP Protection against Confidentiality Attacks and Evolving Role of CAD Tool. 1-8.
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Rajendran, J.
(2022).
Session details: The Role of Graph Neural Networks in Electronic Design Automation
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Patnaik, S., Gohil, V., Guo, H., & Rajendran, J.
(2022).
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. 217-218.
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Gohil, V., Patnaik, S., Guo, H., Kalathil, D., & Rajendran, J. J.
(2022).
DETERRENT. 697-702.
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Nahar, L., Rajendran, J., Makris, Y., & Sechen, C.
(2022).
MTBoM: Metal Trace to Bill of Materials Generation for PCB Reverse Engineering. 1-6.
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Kande, R., Crump, A., Persyn, G., Jauernig, P., Sadeghi, A., Tyagi, A., & Rajendran, J.
(2022).
TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities. 3219-3236.
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Sadeghi, A., Rajendran, J., & Kande, R.
(2021).
Organizing The World's Largest Hardware Security Competition. 95-100.
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Han, Z., Yasin, M., & Rajendran, J.
(2021).
Does logic locking work with EDA tools?. 1055-1072.
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Sanabria-Borbon, A., Jayasankaran, N. G., Lee, S., Sanchez-Sinencio, E., Hu, J., & Rajendran, J.
(2020).
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. International Test Conference.
1-10.
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Han, Z., Yasin, M., & Rajendran, J.
(2020).
Multi-Objective Strategies for Stripped-Functionality Logic Locking. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
1-5.
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Yasin, M., Zhao, C., & Rajendran, J. J.
(2019).
SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
1-4.
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Vrecenar, R., Hall, M., Zshiesche, J., Naidu, M., Rajendran, J. V., & Kalafatis, S.
(2019).
Red Teaming a Multi-colored Bluetooth Bulb. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
293-296.
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Jayasankaran, N. G., Borbon, A. S., Abuellil, A., Sanchez-Sinencio, E., Hu, J., & Rajendran, J.
(2019).
Breaking Analog Locking Techniques via Satisfiability Modulo Theories. International Test Conference.
1-10.
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Silva-Martinez, J., Wang, Y. u., Abdelgawad, A., Rajendran, J., Garrity, D., Easwaran, S. N., ... Setti, G.
(2019).
MWSCAS 2019 Tutorials. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
i-x.
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Salmani, H., Hoque, T., Bhunia, S., Yasin, M., Rajendran, J., & Karimi, N.
(2019).
Special Session: Countering IP Security threats in Supply chain. 1-9.
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Xu, W., Feng, L., Rajendran, J. J., & Hu, J.
(2019).
Layout Recognition Attacks on Split Manufacturing. 45-50.
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Dessouky, G., Gens, D., Haney, P., Persyn, G., Kanuparthi, A., Khattri, H., ... Rajendran, J.
(2019).
HardFails: Insights into Software-Exploitable Hardware Bugs. 213-230.
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Commarota, R. o., Karimi, N., Garg, S., & Rajendran, J.
(2018).
Special Session: Recent Developments in Hardware Security. 1-1.
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Jayasankaran, N. G., Borbon, A. S., Sanchez-Sinencio, E., Hu, J., & Rajendran, J.
(2018).
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
1-8.
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Zaman, M., Sengupta, A., Liu, D., Sinanoglu, O., Makris, Y., & Rajendran, J.
(2018).
Towards Provably-Secure Performance Locking. Proceedings -Design, Automation and Test in Europe, DATE.
1592-1597.
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Broadfoot, T., Sechen, C., & Rajendran, J.
(2017).
On designing optimal camouflaged layouts. 169-169.
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Yasin, M., Mazumdar, B., Rajendran, J., & Sinanoglu, O.
(2017).
TTLock: Tenacious and traceless logic locking. 166-166.
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Rajendran, J.
(2017).
An Overview of Hardware Intellectual Property Protection. IEEE International Symposium on Circuits and Systems.
1-4.
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Di Crescenzo, G., Rajendran, J., Karri, R., & Memon, N.
(2017).
Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization. 7-16.
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Alagappan, M., Rajendran, J., Doroslovaki, M., & Venkataramani.
(2017).
DFS Covert Channels on Multi-Core Platforms. IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC.
1-6.
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Wang, Y., Cao, T., Hu, J., & Rajendran, J.
(2017).
Front-End-of-Line Attacks in Split Manufacturing. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
1-8.
-
Feng, L., Wang, Y., Hu, J., Mak, W., & Rajendran, J.
(2017).
Making Split Fabrication Synergistically Secure and Manufacturable. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
321-328.
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Feng, L., Wang, Y., Hu, J., Mak, W., & Rajendran, J.
(2017).
Making Split Fabrication Synergistically Secure and Manufacturable. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
313-320.
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Yasin, M., Sengupta, A., Nabeel, M. T., Ashraf, M., Rajendran, J., & Sinanoglu, O.
(2017).
Provably-Secure Logic Locking: From Theory To Practice. 1601-1618.
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Yasin, M., Sengupta, A., Nabeel, M. T., Ashraf, M., Rajendran, J., & Sinanoglu, O.
(2017).
Provably-Secure logic locking: From theory to practice. Proceedings of the ACM Conference on Computer and Communications Security.
1601-1618.
-
Wang, Y., Chen, P. u., Hu, J., & Rajendran, J.
(2017).
Routing Perturbation for Enhanced Security in Split Manufacturing. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
605-610.
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Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2017).
Security Analysis of Anti-SAT. 342-347.
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Yasin, M., Sengupta, A., Schafer, B. C., Makris, Y., Sinanoglu, O., & Rajendran, J.
(2017).
What to Lock?. 351-356.
-
Feng, L., Wang, Y., Hu, J., Mak, W., Rajendran, J., & IEEE.
(2017).
Making Split Fabrication Synergistically Secure and Manufacturable. 313-320.
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Feng, L., Wang, Y., Hu, J., Mak, W., Rajendran, J., & IEEE.
(2017).
Making Split Fabrication Synergistically Secure and Manufacturable. 321-328.
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Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2016).
CamoPerturb. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
1-8.
-
Tang, J., Karri, R., & Rajendran, J.
(2016).
Securing Pressure Measurements Using SensorPUFs. IEEE International Symposium on Circuits and Systems.
1330-1333.
-
Yasin, M., Saeed, S. M., Rajendran, J., & Sinanoglu, O.
(2016).
Activation of logic encrypted chips: Pre-test or post-test?. 139-144.
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Kanuparthi, A., Rajendran, J., & Karri, R.
(2016).
Controlling Your Control Flow Graph. 43-48.
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Rajendran, J., Dhandayuthapany, A., Vedula, V., & Karri, R.
(2016).
Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage. Proceedings of the IEEE International Conference on VLSI Design.
547-552.
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Bidmeshki, M., Reddy, G. R., Zhou, L., Rajendran, J., & Makris, Y.
(2016).
Hardware-Based Attacks to Compromise the Cryptographic Security of an Election System. 153-156.
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Yasin, M., Mazumdar, B., Rajendran, J., & Sinanoglu, O.
(2016).
SARLock: SAT Attack Resistant Logic Locking. 236-241.
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Yang, C., Liu, B., Li, H., Chen, Y., Wen, W., Barnell, M., Wu, Q., & Rajendran, J.
(2016).
Security of neuromorphic computing. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
1-6.
-
Majumder, B., Uddin, M., Rose, G. S., & Rajendran, J.
(2016).
Sneak Path Enabled Authentication for Memristive Crossbar Memories. 1-6.
-
Wang, Y., Chen, P. u., Hu, J., & Rajendran, J.
(2016).
The Cat and Mouse in Split Manufacturing. Design Automation Conference.
1-6.
-
Rajendran, J., Vedula, V., & Karri, R.
(2015).
Detecting malicious modifications of data in third-party intellectual property cores. Design Automation Conference.
1-6.
-
Waksman, A., Rajendran, J., Suozzo, M., & Sethumadhavan, S.
(2014).
A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. Design Automation Conference.
1-4.
-
Waksman, A., Rajendran, J., Suozzo, M., & Sethumadhavan, S.
(2014).
A Red Team/Blue Team Assessment of Functional Analysis Methods for Malicious Circuit Identification. 1-4.
-
Natarajan, S., Majumdar, A., & Rajendran, J.
(2014).
Hot topic session 9C: Test and fault tolerance for emerging memory technologies. 1-1.
-
Shahrjerdi, D., Rajendran, J., Garg, S., Koushanfar, F., & Karri, R.
(2014).
Shielding and Securing Integrated Circuits with Sensors. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
170-174.
-
Hoe, D., Rajendran, J., & Karri, R.
(2014).
Towards secure analog designs: a secure sense amplifier using memristors. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI.
516-521.
-
Zhang, X., Xiao, K., Tehranipoor, M., Rajendran, J., & Karri, R.
(2013).
A study on the effectiveness of trojan detection techniques using a red team blue team approach. 1-3.
-
Rose, G. S., Rajendran, J., McDonald, N., Karri, R., Potkonjak, M., & Wysocki, B.
(2013).
Hardware Security Strategies Exploiting Nanoelectronic anoelectronic Circuits. 368-372.
-
Rostami, M., Koushanfar, F., Rajendran, J., & Karri, R.
(2013).
Hardware Security: Threat Models and Metrics. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
819-823.
-
Rajendran, J., Zhang, H., Sinanoglu, O., & Karri, R.
(2013).
High-Level Synthesis for Security and Trust. 232-233.
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Sinanoglu, O., Karimi, N., Rajendran, J., Karri, R., Jin, Y., Huang, K., & Makris, Y.
(2013).
Reconciling the IC Test and Security Dichotomy. 1-6.
-
Liu, C., Rajendran, J., Yang, C., & Karri, R.
(2013).
Shielding Heterogeneous MPSoCs from Untrustworthy 3PIPs through Security-Driven Task Scheduling. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
101-106.
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Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O.
(2013).
Sneak-path Testing of Memristor-based Memories. Proceedings of the IEEE International Conference on VLSI Design.
386-391.
-
Rajendran, J., Sinanoglu, O., & Karri, R.
(2013).
VLSI Testing based Security Metric for IC Camouflaging. International Test Conference.
1-4.
-
Rajendran, J., Sinanoglu, O., & Karri, R.
(2013).
Is Split Manufacturing Secure?. Proceedings -Design, Automation and Test in Europe, DATE.
1259-1264.
-
Rajendran, J., Sam, M., Sinanoglu, O., & Karri, R.
(2013).
Security analysis of integrated circuit camouflaging. Proceedings of the ACM Conference on Computer and Communications Security.
709-720.
-
Kannan, S., Rajendran, J., Karri, R., & Sinanoglu, O.
(2012).
Engineering Crossbar based Emerging Memory Technologies. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
478-479.
-
Rajendran, J., Pino, Y., Sinanoglu, O., & Karri, R.
(2012).
Security analysis of logic obfuscation. Design Automation Conference.
83-89.
-
Rajendran, J., Pino, Y., Sinanoglu, O., & Karri, R.
(2012).
Logic encryption: A fault analysis perspective. Proceedings -Design, Automation and Test in Europe, DATE.
953-958.
-
Rajendran, J., Rose, G. S., Karri, R., & Potkonjak, M.
(2012).
Nano-PPUF: A Memristor-based Security Primitive. 84-87.
-
Rajendran, J., Maenm, H., Karri, R., & Rose, G. S.
(2011).
An Approach to Tolerate Process Related Variations in Memristor-Based Applications. Proceedings of the IEEE International Conference on VLSI Design.
18-23.
-
Rajendran, J., Jyothi, V., & Karri, R.
(2011).
Blue team red team approach to hardware trust assessment. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
285-288.
-
Rajendran, J., Jyothi, V., Sinanoglu, O., & Karri, R.
(2011).
Design and Analysis of Ring Oscillator based Design-for-Trust technique. 105-110.
-
Rajendran, J., Karri, R., & Rose, S. G.
(2011).
Parallel Memristors: Improving Variation Tolerance in Memristive Digital Circuits. IEEE International Symposium on Circuits and Systems.
2241-2244.
-
Rajendran, J., Gavas, E., Jimenez, J., Padman, V., & Karri, R.
(2010).
Towards a comprehensive and systematic classification of hardware Trojans. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
1871-1874.
-
Rajendran, J., Manem, H., Karri, R., & Rose, G. S.
(2010).
Memristor based Programmable Threshold Logic Array. 5-10.
-
Rajendran, J., Borad, H., Mantravadi, S., & Karri, R.
(2010).
SLICED: Slide-based concurrent error detection technique for symmetric block ciphers. 70-75.
-
Rajendran, J., Manem, H., & Rose, G. S.
(2009).
NDR based threshold logic fabric with memristive synapses. 725-728.
-
Chandrasekaran, S., Rajendran, J., & Annamalai, A.
(2008).
Data Driven Security Alarm Model for Embedded Applications. 1-5.
-
Rostami, M., Zeitouni, S., Kande, R., Chen, C., Mahmoody, P., Rajendran, J., & Sadeghi, A.
Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection. 1-6.
-
Ku, J., Zhang, J., Shan, H., Samudrala, S., Wu, J., Zheng, Q., ... Chen, Y.
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM. 1-6.
-
Gohil, V., Guo, H., Patnaik, S., & Rajendran, J.
(2022).
ATTRITION: Attacking Static Hardware Trojan Detection Techniques Using Reinforcement Learning. 1275-1289.
-
institutional repository document
-
Tyagi, A., Crump, A., Sadeghi, A., Persyn, G., Rajendran, J., Jauernig, P., & Kande, R.
(2022).
TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities
-
Tan, B., Karri, R., Limaye, N., Sengupta, A., Sinanoglu, O., Rahman, M. M., ... Plaks, K.
(2020).
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking
-
Jin, C., Gohil, V., Karri, R., & Rajendran, J.
(2020).
Security of Cloud FPGAs: A Survey
-
Dessouky, G., Gens, D., Haney, P., Persyn, G., Kanuparthi, A., Khattri, H., ... Rajendran, J.
(2018).
When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs
-
Jayasankaran, N. G., Sanabria-Borbon, A. C., Snchez-Sinencio, E., Hu, J., & Rajendran, J.
(2018).
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction
-
Dessouky, G., Gens, D., Haney, P., Persyn, G., Kanuparthi, A. K., Khattri, H., ... Rajendran, J.
(2018).
When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs
-
Yasin, M., Mazumdar, B., Sinanoglu, O., & Rajendran, J.
(2016).
Security Analysis of Anti-SAT
-
Yasin, M., Sinanoglu, O., & Rajendran, J.
(2016).
Testing the Trustworthiness of IC Testing: An Oracle-less Attack on IC Camouflaging
-
Rajendran, J., Karri, R., Wendt, J. B., Potkonjak, M., McDonald, N. R., Rose, G. S., & Wysocki, B. T.
(2012).
Nanoelectronic Solutions for Hardware Security
-
Tyagi, A., Crump, A., Sadeghi, A., Persyn, G., Rajendran, J., Jauernig, P., & Kande, R.
(2022).
TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities
-
patent
-
Rajendran, J., Hu, J., Wang, Y., & Chen, P. u.
(2020).
Defense techniques for split manufacturing
-
Rajendran, J., Hu, J., Wang, Y., & Chen, P. u.
(2020).
Defense techniques for split manufacturing
Research
principal investigator on
- Collaborative Research: EAGER: SaTC-EDU: Dynamic Adaptive Machine Learning for Teaching Hardware Security (DYNAMITES) awarded by Directorate for Education & Human Resources - (Arlington, Virginia, United States) 2020 - 2022
- CAREER: Towards Provably-Secure Design of Integrated Circuits awarded by National Science Foundation - (Arlington, Virginia, United States) 2017 - 2022
- Towards verification-guided hardware synthesis for security awarded by United States Department of the Navy - (Arlington, Virginia, United States) 2018 - 2021
- EAGER: Collaborative: Secure and Trustworthy Cyberphysical Microfluidic Systems awarded by National Science Foundation - (Arlington, Virginia, United States) 2018 - 2020
- Secure System-on-Chip Challenge: A Red Team-Blue Team Stress Test for State-of-the-Art System-on-Chip Designs awarded by United States Army - (Washington D.C., District of Columbia, United States) 2018 - 2019
- STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs awarded by National Science Foundation - (Arlington, Virginia, United States) 2017 - 2019
co-principal investigator on
Teaching
teaching activities
- ECEN248 Intro To Dgtl Sym Dsgn Instructor
- ECEN403 Electrical Design Lab I Instructor
- ECEN404 Hnr-electrical Design Lab Ii Instructor
- ECEN426 Security Of Embedded Systems Instructor
- ECEN454 Dig Integratedckt Des Instructor
- ECEN489 Sptp: Security Embedded Sys Instructor
- ECEN489 Sptp:security Embedded Sys Instructor
- ECEN491 Research Instructor
- ECEN684 Professional Internship Instructor
- ECEN685 Directed Studies Instructor
- ECEN689 Sptp: Sec Val & Verif Com Sys Instructor
- ECEN689 Sptp:harware Security Instructor
- ECEN691 Research Instructor
- ECEN714 Digital Integrated Circuit Des Instructor
- ECEN759 Hardware Security Instructor
Background
education and training
- Ph.D. in Electrical Engineering, New York University - (New York, New York, United States) 2015
- M.S. in Computer Engineering, New York University - (New York, New York, United States) 2011
- B.E. in Electronics and Communication Engineering, Anna University, Chennai - (Chennai, Tamil Nadu, India) 2008
awards and honors
Contact
first name
- Jeyavijayan
has last name
- Rajendran
mailing address
-
Texas A&M University
Electrical Engineering
3128 TAMU
College Station, TX 77843-3128
USA
Other
- jeyavijayan@tamu.edu