Memristor based Programmable Threshold Logic Array Conference Paper

abstract

• In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty. 2010 IEEE.

name of conference

• 2010 IEEE/ACM International Symposium on Nanoscale Architectures

authors

• Rajendran, Jeyavijayan

published proceedings

• 2010 IEEE/ACM International Symposium on Nanoscale Architectures

author list (cited authors)

• Rajendran, J., Manem, H., Karri, R., & Rose, G. S.

citation count

• 43

complete list of authors

• Rajendran, Jeyavijayan||Manem, Harika||Karri, Ramesh||Rose, Garrett S

publication date

• January 2010

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/nanoarch.2010.5510933

International Standard Book Number (ISBN) 13

• 9781424480180

start page

• 5

end page

• 10

URL

• http://dx.doi.org/10.1109/nanoarch.2010.5510933