VLSI testing based security metric for IC camouflaging Conference Paper uri icon

abstract

  • An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor. © 2013 IEEE.

name of conference

  • 2013 IEEE International Test Conference (ITC)

published proceedings

  • 2013 IEEE International Test Conference (ITC)

author list (cited authors)

  • Rajendran, J., Sinanoglu, O., & Karri, R.

citation count

  • 29

complete list of authors

  • Rajendran, Jeyavijayan||Sinanoglu, Ozgur||Karri, Ramesh

publication date

  • September 2013

publisher