VLSI Testing based Security Metric for IC Camouflaging Conference Paper

abstract

• An Integrated Circuit (IC) can be reverse engineered by imaging its layout and reconstructing the netlist. IC camouflaging is a layout-level technique that hampers imaging-based reverse engineering by using, in one embodiment, functionally different standard cells that look alike. Reverse engineering will fail if the functionality of a camouflaged gate cannot be correctly resolved. We adapt VLSI testing principles (justification and sensitization) to quantify the ability of a reverse engineer to unambiguously resolve the functionality of look-alike camouflaged gates. We evaluate the security of look-alike standard cells based IC camouflaging by applying it on the controllers in OpenSPARC T1 processor. 2013 IEEE.

name of conference

• 2013 IEEE International Test Conference (ITC)

authors

• Rajendran, Jeyavijayan

published proceedings

• 2013 IEEE International Test Conference (ITC)

author list (cited authors)

• Rajendran, J., Sinanoglu, O., & Karri, R.

citation count

• 29

complete list of authors

• Rajendran, Jeyavijayan||Sinanoglu, Ozgur||Karri, Ramesh

publication date

• January 2013

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International Test Conference  Journal

Digital Object Identifier (DOI)

• 10.1109/test.2013.6651879

International Standard Book Number (ISBN) 13

• 9781479908592

start page

• 1

end page

• 4

URL

• http://dx.doi.org/10.1109/test.2013.6651879