Pre-SAT Logic Locking Chapter

authors

• Rajendran, Jeyavijayan

author list (cited authors)

• Yasin, M., Rajendran, J., & Sinanoglu, O.

complete list of authors

• Yasin, Muhammad||Rajendran, Jeyavijayan JV||Sinanoglu, Ozgur

Book Title

• TRUSTWORTHY HARDWARE DESIGN: COMBINATIONAL LOGIC LOCKING TECHNIQUES

publication date

• 2020

publisher

• Springer International Publishing  Publisher

published in

• n1872-082XISSN  Journal

Digital Object Identifier (DOI)

• 10.1007/978-3-030-15334-2_3

International Standard Book Number (ISBN) 13

• 978-3-030-15333-5

start page

• 33

end page

• 46

URL

• http://dx.doi.org/10.1007/978-3-030-15334-2_3