Breaking Analog Locking Techniques Academic Article

authors

• Rajendran, Jeyavijayan

published proceedings

• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

author list (cited authors)

• Jayasankaran, N. G., Sanabria-Borbon, A., Abuellil, A., Sanchez-Sinencio, E., Hu, J., & Rajendran, J.

citation count

• 11

complete list of authors

• Jayasankaran, Nithyashankari Gummidipoondi||Sanabria-Borbon, Adriana||Abuellil, Amr||Sanchez-Sinencio, Edgar||Hu, Jiang||Rajendran, Jeyavijayan

publication date

• October 2020

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• Analog Circuits
• Analog Locking
• Delays
• Hardware Security
• Integrated Circuits
• Ip Protection
• Layout
• Logic Locking
• Threshold Voltage
• Transistors
• Voltage Control

Digital Object Identifier (DOI)

• 10.1109/TVLSI.2020.3007159

start page

• 2157

end page

• 2170

volume

• 28

issue

• 10

URL

• http://dx.doi.org/10.1109/tvlsi.2020.3007159