Reconciling the IC Test and Security Dichotomy Conference Paper uri icon

abstract

  • Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs. 2013 IEEE.

name of conference

  • 2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)

published proceedings

  • 2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)

altmetric score

  • 3

author list (cited authors)

  • Sinanoglu, O., Karimi, N., Rajendran, J., Karri, R., Jin, Y., Huang, K., & Makris, Y.

citation count

  • 23

complete list of authors

  • Sinanoglu, O||Karimi, N||Rajendran, J||Karri, R||Jin, Y||Huang, K||Makris, Y

publication date

  • January 2013