Keynote: A Disquisition on Logic Locking Academic Article

authors

• Rajendran, Jeyavijayan

published proceedings

• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

altmetric score

• 3

author list (cited authors)

• Chakraborty, A., Jayasankaran, N. G., Liu, Y., Rajendran, J., Sinanoglu, O., Srivastava, A., ... Zuzak, M.

citation count

• 60

complete list of authors

• Chakraborty, Abhishek||Jayasankaran, Nithyashankari Gummidipoondi||Liu, Yuntao||Rajendran, Jeyavijayan||Sinanoglu, Ozgur||Srivastava, Ankur||Xie, Yang||Yasin, Muhammad||Zuzak, Michael

publication date

• October 2020

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Journal

keywords

• Boolean Satisfiability (sat)
• Design-for-security
• Fabrication
• Foundries
• Hardware
• Hardware Supply Chain Security
• Integrated Circuits
• Intellectual Property (ip) Protection
• Logic Locking
• Security
• Supply Chains

Digital Object Identifier (DOI)

• 10.1109/TCAD.2019.2944586

start page

• 1952

end page

• 1972

volume

• 39

issue

• 10

URL

• http://dx.doi.org/10.1109/tcad.2019.2944586