NDR based threshold logic fabric with memristive synapses Conference Paper uri icon


  • In recent years, many researchers have proposed the usage of molecular scale devices exhibiting negative differential resistance (NDR) in the realization of programmable logic circuitry. This paper deals with the utilization of one such system built from NDR based circuitry, specifically the Goto pair, in the implementation of a programmable threshold logic array (PTLA). Furthermore, the PTLA considered here uses memristors exhibiting multiple levels of resistance to provide weighted inputs to each threshold gate. Circuit level considerations for the Goto pair to be implemented as part of PTLA are discussed. An image classification application is also implemented using the proposed PTLA and simulated for functionality and performance using Cadence Spectre. 2009 IEEE NANO Organizers.

published proceedings

  • 2009 9th IEEE Conference on Nanotechnology, IEEE NANO 2009

author list (cited authors)

  • Rajendran, J., Manem, H., & Rose, G. S.

publication date

  • January 2009