Security analysis of integrated circuit camouflaging Conference Paper uri icon

abstract

  • Camouflaging is a layout-level technique that hampers an attacker from reverse engineering by introducing, in one embodiment, dummy contacts into the layout. By using a mix of real and dummy contacts, one can camouflage a standard cell whose functionality can be one of many. If an attacker cannot resolve the functionality of a camouflaged gate, he/she will extract an incorrect netlist. In this paper, we analyze the feasibility of identifying the functionality of camouflaged gates. We also propose techniques to make the dummy contact-based IC camouflaging technique resilient to reverse engineering. Furthermore, we judiciously select gates to camouflage by using techniques which ensure that the outputs of the extracted netlist are controllably corrupted. The techniques leverage IC testing principles such as justification and sensitization. The proposed techniques are evaluated using ISCAS benchmark circuits and OpenSparc T1 microprocessor controllers. 2013 ACM.

name of conference

  • Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security - CCS '13

published proceedings

  • Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security - CCS '13

altmetric score

  • 3

author list (cited authors)

  • Rajendran, J., Sam, M., Sinanoglu, O., & Karri, R.

citation count

  • 277

complete list of authors

  • Rajendran, Jeyavijayan||Sam, Michael||Sinanoglu, Ozgur||Karri, Ramesh

publication date

  • January 2013