Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage Conference Paper

abstract

• 2016 IEEE. Globalization of the system-on-chip (SoC) design flow has created opportunities for rogue intellectual property (IP) vendors to insert malicious circuits (a.k.a. hardware Trojans) into their IPs. We propose to formally verify third party IPs (3PIPs) for unauthorized information leakage. We validate our technique using Trojan benchmarks from the Trust-Hub.

name of conference

• 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)

authors

• Rajendran, Jeyavijayan

published proceedings

• 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID)

author list (cited authors)

• Rajendran, J., Dhandayuthapany, A., Vedula, V., & Karri, R.

citation count

• 40

complete list of authors

• Rajendran, J||Dhandayuthapany, A||Vedula, V||Karri, R

publication date

• January 2016

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the IEEE International Conference on VLSI Design  Journal

Digital Object Identifier (DOI)

• 10.1109/vlsid.2016.143

International Standard Book Number (ISBN) 13

• 9781467387002

start page

• 547

end page

• 552

volume

• 2016-March

URL

• http://dx.doi.org/10.1109/vlsid.2016.143