Parallel Memristors: Improving Variation Tolerance in Memristive Digital Circuits Conference Paper

abstract

• Memristors are employed by a wide variety of applications such as neural networks, memory and digital logic. However, the process variation effects of memristors may affect these applications. In this research, we consider the effect of process variations in the thickness of the oxide layer of memristors that are used in Memristor-based Threshold Logic (MTL) gates. As the effect of variations is less pronounced in high memristance values, a variation tolerant design without any degradation in speed is achieved by having a number of high memristance devices in parallel (redundancy factor). We propose an algorithm for the MTL gates to determine the number of memristors in parallel and the variation-minimal high memristance state. A power optimization algorithm is also proposed to map gates in a design using different libraries that have different performance characteristics. Finally, we present the power, delay performance and also the redundancy factor of memristors for various benchmark circuits. 2011 IEEE.

name of conference

• 2011 IEEE International Symposium of Circuits and Systems (ISCAS)

authors

• Rajendran, Jeyavijayan

published proceedings

• 2011 IEEE International Symposium of Circuits and Systems (ISCAS)

author list (cited authors)

• Rajendran, J., Karri, R., & Rose, S. G.

citation count

• 5

complete list of authors

• Rajendran, Jeyavijayan||Karri, Ramesh||Rose, S Garrett

publication date

• January 2011

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Symposium on Circuits and Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/iscas.2011.5938047

International Standard Book Number (ISBN) 13

• 9781424494736

start page

• 2241

end page

• 2244

URL

• http://dx.doi.org/10.1109/iscas.2011.5938047