A placement methodology for robust clocking Conference Paper

abstract

• As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in performance optimization. This work proposes a new placement methodology that facilitates low cost and robust clock network. It is based on the observation that bringing tightly constrained flip-flops close to each other can reduce the non-common paths between them in clock network. Such a reduction will in-turn improve the tolerance of the clock network towards variations in delay/skew. Monte Carlo experiments (based on spatial correlations) indicate that our methodology can reduce the maximum skew violation due to variations by up to 62% with less than 2.7% increase in total wire length. 2007 IEEE.

name of conference

• 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)

authors

• Hu, Jiang

published proceedings

• 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS

author list (cited authors)

• Venkataraman, G., & Hu, J.

citation count

• 3

complete list of authors

• Venkataraman, Ganesh||Hu, Jiang

publication date

• January 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the IEEE International Conference on VLSI Design  Journal

keywords

• 40 Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/VLSID.2007.20

International Standard Book Number (ISBN) 10

• 0769527620

International Standard Book Number (ISBN) 13

• 978-0-7695-2762-8

start page

• 881

end page

• +

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fvlsid.2007.20