A Placement Methodology for Robust Clocking**This work was supported in part by Semiconductor Research Corporation under contract number 2004- TJ-1205.
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As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in performance optimization. This work proposes a new placement methodology that facilitates low cost and robust clock network. It is based on the observation that bringing tightly constrained flip-flops close to each other can reduce the non-common paths between them in clock network. Such a reduction will in-turn improve the tolerance of the clock network towards variations in delay/skew. Monte Carlo experiments (based on spatial correlations) indicate that our methodology can reduce the maximum skew violation due to variations by up to 62% with less than 2.7% increase in total wire length. © 2007 IEEE.
author list (cited authors)
Venkataraman, G., & Hu, J.