A multilayered VLSI array design for multistage interconnection network Conference Paper uri icon

abstract

  • 1991 IEEE. The multilayered 3D design of an indirect binary N-cube (IBNC) multistage interconnection network (MIN) is presented. The implementation of IBNC MIN in the form of a multilayered array seems to be attractive due to less conventional connections than that in its systolic implementation approach. The area and delay performance is also found to be better compared to other two methods of implementation.

name of conference

  • [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

published proceedings

  • [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design

author list (cited authors)

  • Mahapatra, R. N., & Kar, B. K.

citation count

  • 0

complete list of authors

  • Mahapatra, RN||Kar, BK

publication date

  • January 1991