A Hardware Scheduler for Real Time Multiprocessor System on Chip
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This paper presents the design and implementation of a low-power hardware scheduler for multiprocessor system-on-chips. The Pfair scheduling algorithm is considered with three different implementation schemes: replicated software scheduler running on each processor, single software scheduler running on a dedicated processor and the proposed hardware scheduler. Experimental evaluation with benchmarks shows that the hardware scheduler outperforms the other two schemes in terms of energy consumption by an order of magnitude of 10 5 and scheduling delay by an order of magnitude of 103. 2010 IEEE.
name of conference
2010 23rd International Conference on VLSI Design: concurrently with the 9th International Conference on Embedded Systems Design (VLSID)
2010 23rd International Conference on VLSI Design
author list (cited authors)
Gupta, N., Mandal, S. K., Malave, J., Mandal, A., & Mahapatra, R. N.
complete list of authors
Gupta, Nikhil||Mandal, Suman K||Malave, Javier||Mandal, Ayan||Mahapatra, Rabi N