A Hardware Scheduler for Real Time Multiprocessor System on Chip Conference Paper

abstract

• This paper presents the design and implementation of a low-power hardware scheduler for multiprocessor system-on-chips. The Pfair scheduling algorithm is considered with three different implementation schemes: replicated software scheduler running on each processor, single software scheduler running on a dedicated processor and the proposed hardware scheduler. Experimental evaluation with benchmarks shows that the hardware scheduler outperforms the other two schemes in terms of energy consumption by an order of magnitude of 10 5 and scheduling delay by an order of magnitude of 103. 2010 IEEE.

name of conference

• 2010 23rd International Conference on VLSI Design

authors

• Mahapatra, Rabinarayan

published proceedings

• 2010 23rd International Conference on VLSI Design

author list (cited authors)

• Gupta, N., Mandal, S. K., Malave, J., Mandal, A., & Mahapatra, R. N.

citation count

• 16

complete list of authors

• Gupta, Nikhil||Mandal, Suman K||Malave, Javier||Mandal, Ayan||Mahapatra, Rabi N

publication date

• January 2010

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the IEEE International Conference on VLSI Design  Journal

Digital Object Identifier (DOI)

• 10.1109/vlsi.design.2010.43

International Standard Book Number (ISBN) 13

• 9780769539287

start page

• 264

end page

• 269

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fvlsi.design.2010.43