A memory-efficient hashing by multi-predicate bloom filters for packet classification Conference Paper uri icon

abstract

  • Hash tables (HTs) are poorly designed for multiple off-chip memory accesses during packet classification and critically affect throughput in high-speed routers. Therefore, an HT with fast on-chip memory and high-capacity off-chip memory for predictable lookup-throughput is desirable. Both a legacy HT (LHT) and a recently proposed fast HT (FHT) [1] have the disadvantage of memory overhead due to pointers and duplicate items in linked lists. Also, memory usage for an FHT did not consider the bits in counters for fair comparision with an LHT. In this paper, we propose a novel hash architecture called a Multi predicate Bloom-filtered HT (MBHT) using parallel Bloom filters and generating off-chip memory addresses in the base-2x number system, x∈{1, 2, ⋯}, which removes the overhead of pointers. Using a larger base of number system, an MBHT reduces on-chip memory size by a factor of log 2 b2 / log2 b1 where b1 and b2 are bases of number system (b2>b1). Compared to an FHT, the MBHT is approximately x(log2 n + 4)/ (2 log2 n) times more efficient for on-chip memory, where n is the number of keys. This results in a significant reduction in the number of off-chip memory accesses. A simulation with a dataset of packets from NLANR [2] shows the on-chip memory reductions by 1.7 and 2 times over an LHT and an FHT are made. Besides, an MBHT of base-16 needs less off-chip memory accesses by 2117 in total URL queries of NLANR, compared to an FHT. © 2008 IEEE.

author list (cited authors)

  • Yu, H., Mahapatra, R., & IEEE, ..

publication date

  • January 1, 2008 11:11 AM

publisher