Antenna avoidance in layer assignment Conference Paper

abstract

• The sustained progress of very-large-scale-integration (VLSI) technology has dramatically increased the likelihood of the antenna problem in the manufacturing process and calls for corresponding considerations in the routing stage. In this paper, the authors propose a technique that can handle the antenna problem during the layer-assignment (LA) stage, which is an important step between global routing and detailed routing. The antenna-avoidance problem is modeled as a tree-partitioning problem with a linear-time-optimal-algorithm solution. This algorithm is customized to guide antenna avoidance in the LA stage. A linear-time optimal jumper-insertion algorithm is also derived. Experimental results on benchmark circuits show that the proposed techniques can lead to an average of 76% antenna-violation reduction and 99% via-violation reduction. 2006 IEEE.

authors

• Hu, Jiang
• Mahapatra, Rabinarayan

published proceedings

• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

author list (cited authors)

• Wu, D., Hu, J., & Mahapatra, R. N.

citation count

• 18

complete list of authors

• Wu, D||Hu, J||Mahapatra, RN

publication date

• April 2006

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Journal

keywords

• Antenna Effect
• Interconnect
• Layer Assignment (la)
• Physical Design
• Very Large Scale Integration (vlsi)

Digital Object Identifier (DOI)

• 10.1109/TCAD.2006.870061

start page

• 734

end page

• 738

volume

• 25

issue

• 4

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftcad.2006.870061