Low power nanoscale buffer management for network on chip routers Conference Paper uri icon

abstract

  • Network-on-Chip (NoC) is an on-chip communication solution in the future system-on-a-chip (SoC) necessitating high performance operation with low power dissipation. We present a novel dynamic power management technique for low power NoC router buffers using nano CMOS SRAMS. A feedback controller was designed for block level power management and a power aware adaptive controller was designed for low power flit storage encoding to reduce energy consumptions in the router buffers. Experiments with the proposed scheme showed up to 20% reduction in energy consumption while improving throughput by up to 21%. 2010 ACM.

name of conference

  • Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10

published proceedings

  • Proceedings of the 20th symposium on Great lakes symposium on VLSI - GLSVLSI '10

author list (cited authors)

  • Mandal, S. K., Denton, R., Mohanty, S. P., & Mahapatra, R. N.

citation count

  • 2

complete list of authors

  • Mandal, Suman K||Denton, Ron||Mohanty, Saraju P||Mahapatra, Rabi N

publication date

  • January 2010