An Efficient Approach to On-Chip Logic Minimization Academic Article uri icon


  • Boolean logic minimization is being applied increasingly to a new variety of applications that demand very fast and frequent minimization services. These applications typically have access to very limited computing and memory resources, rendering the traditional logic minimizers ineffective. We present a new approximate logic minimization algorithm based on ternary trie. We compare its performance with Espresso-II and ROCM logic minimizers for routing table compaction and demonstrate that it is 100 to 1000 times faster and can execute with a data memory as little as 16 KB. We also found that the proposed approach can support up to 25 000 incremental updates per second. We also compare its performance for compaction of the routing access control list and demonstrate that the proposed approach is highly suitable for minimizing large access control lists containing several thousand entries. Therefore, the algorithm is ideal for on-chip logic minimization. 2007 IEEE.

published proceedings

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

author list (cited authors)

  • Ahmad, S., & Mahapatra, R. N.

citation count

  • 6

complete list of authors

  • Ahmad, Seraj||Mahapatra, Rabi N

publication date

  • September 2007