IEEE Transactions on Very Large Scale Integration Systems Journal

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Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation. 29:1693-1706. 2021
Formal Modeling and Verification of PCHB Asynchronous Circuits. 27:2911-2924. 2019
SRMC: A Multibit Memristor Crossbar for Self-Renewing Image Mask. 26:2830-2841. 2018
A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications. 26:1192-1203. 2018
The Cat and Mouse in Split Manufacturing. 26:805-817. 2018
A Continuous-Time MASH 1-1-1 DeltaSigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS. 26:756-767. 2018
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. 24:2946-2959. 2016
Design for Testability of Sleep Convention Logic. 24:743-753. 2016
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain. 23:198-202. 2015
Boostable Repeater Design for Variation Resilience in VLSI Interconnects. 21:1619-1631. 2013
A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures. 21:1421-1431. 2013
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 $mu$m CMOS. 20:564-568. 2012
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. 18:1639-1648. 2010
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. 18:1471-1482. 2010
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. 18:1025-1035. 2010
Pattern Sensitive Placement Perturbation for Manufacturability. 18:1002-1006. 2010
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. 18:29-38. 2010
Combinatorial Algorithms for Fast Clock Mesh Optimization. 18:131-141. 2010
Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture. 18:15-28. 2010
Clock Buffer Polarity Assignment for Power Noise Reduction. 17:770-780. 2009
Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture. 17:593-603. 2009
Efficient On-Chip Crosstalk Avoidance CODEC Design. 17:551-560. 2009
Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. 17:439-443. 2009
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. 17:269-277. 2009
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. 16:1657-1665. 2008
Dynamically de-skewable clock distribution methodology. 16:1220-1229. 2008
Robust Concurrent Online Testing of Network-on-Chip-Based SoCs. 16:1199-1209. 2008
A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic. 16:326-331. 2008
Wire sizing and spacing for lithographic printability and timing optimization. 15:1332-1340. 2007
Enhanced leakage reduction techniques using intermediate strength power gating. 15:1215-1224. 2007
Utilizing redundancy for timing critical interconnect. 15:1067-1080. 2007
An Efficient Approach to On-Chip Logic Minimization. 15:1040-1050. 2007
A predictably low-leakage ASIC design style. 15:276-285. 2007
Integrated placement and skew optimization for rotary clocking. 15:149-157. 2007
Probabilistic Delay Budget Assignment for Synthesis of Soft Real-Time Applications. 14:843-853. 2006
An efficient merging scheme for prescribed skew clock routing. 13:750-754. 2005
EFFICIENT NETWORK FOLDING TECHNIQUES FOR ROUTING PERMUTATIONS IN VLSI. 3:254-263. 1995
Optimal interconnect diagnosis of wiring networks. 3:430-436. 1995
On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements. 1:76-79. 1993
Data Handling Limits of On-Chip Interconnects 2008
Integrated placement and skew optimization for rotary clocking 2007