Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations Academic Article

abstract

• In hardware implementations of many signal processing functions, timing errors on different circuit signals may have largely different importance with respect to the overall signal processing performance. This motivates us to apply the concept of unequal error tolerance to enable the use of voltage overscaling at minimal signal processing performance degradation. Realization of unequal error tolerance involves two main issues, including how to quantify the importance of each circuit signal and how to incorporate the importance quantification into signal processing circuit design. We developed techniques to tackle these two issues and applied them to two types of trellis decoders including Viterbi decoder for convolutional code decoding and Max-Log-Maximum A Posteriori (MAP) decoder for Turbo code decoding. Simulation results demonstrated promising energy saving potentials of the proposed design solution on both trellis decoding computation and memory storage at small decoding performance degradation. 2006 IEEE.

authors

• Hu, Jiang

published proceedings

• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

author list (cited authors)

• Liu, Y., Zhang, T., & Hu, J.

citation count

• 7

complete list of authors

• Liu, Yang||Zhang, Tong||Hu, Jiang

publication date

• March 2009

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Very Large Scale Integration Systems  Journal

keywords

• Clock Skew Scheduling
• Low-power
• Process Variations
• Trellis Decoders
• Unequal Error Tolerance
• Voltage Overscaling (vos)

Digital Object Identifier (DOI)

• 10.1109/TVLSI.2008.2004545

start page

• 439

end page

• 443

volume

• 17

issue

• 3

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftvlsi.2008.2004545

user-defined tag

• 7 Affordable and Clean Energy