Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture Academic Article

abstract

• Coarse-grained reconfigurable architectures (CGRAs) aim to achieve both goals of high performance and flexibility. In addition, power consumption is significant for the reconfigurable architecture to be used as a competitive processing core in embedded systems. However, the existing reconfigurable architectures require too much area and power. In this paper, we propose a new design space exploration flow, optimizing CGRA to reduce area and power with enhancing performance for digital signal processing (DSP) application domain. It reduces the array size through efficient arrangement of array components and customization of their interconnection, exploiting input patterns belonging to the DSP application domain. Such a design flow is based on pipelining and sharing of area/delay-critical resources in the processing element array. Experimental results show that for DSP applications, the proposed approach reduces area by up to 36.75%, average execution time by 36.78%, and average power by 31.85% when compared with the existing CGRA architecture. 2006 IEEE.

authors

• Mahapatra, Rabinarayan

published proceedings

• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

author list (cited authors)

• Kim, Y., Mahapatra, R. N., & Choi, K.

citation count

• 27

complete list of authors

• Kim, Yoonjin||Mahapatra, Rabi N||Choi, Kiyoung

publication date

• October 2010

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Very Large Scale Integration Systems  Journal

keywords

• Coarse-grained Reconfigurable Architecture (cgra)
• Embedded Systems
• Loop Pipelining
• Low Power
• System On Chip (soc)

Digital Object Identifier (DOI)

• 10.1109/TVLSI.2009.2025280

start page

• 1471

end page

• 1482

volume

• 18

issue

• 10

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftvlsi.2009.2025280