A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 $mu$m CMOS Academic Article uri icon


  • A digital delay-locked loop (DLL) suitable for generation of multiphase clocks in applications such as time-interleaved and pipelined analog-to-digital converters (ADCs) locks in a very wide (40) frequency range. The DLL provides 12 uniformly delayed phases, free of false harmonic locking. A two-stage digital split-control loop is implemented: a fast-locking coarse acquisition is achieved in four cycles using binary search; a fine linear loop achieves low jitter (9 ps rms @ 600 MHz) and tracks process, voltage, and temperature (PVT) variations. The false harmonic locking detector, the frequency range and the jitter performance among other design considerations are analyzed in detail. The DLL consumes 20 mW and occupies a 470 m 800 m in 0.13 m CMOS. 2011 IEEE.

published proceedings

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

author list (cited authors)

  • Hoyos, S., Tsang, C. W., Vanderhaegen, J., Chiu, Y., Aibara, Y., Khorramabadi, H., & Nikolic, B.

citation count

  • 13

complete list of authors

  • Hoyos, Sebastian||Tsang, Cheongyuen W||Vanderhaegen, Johan||Chiu, Yun||Aibara, Yasutoshi||Khorramabadi, Haideh||Nikolic, Borivoje

publication date

  • March 2012