Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture Academic Article

abstract

• Most of the coarse-grained reconfigurable architectures (CGRAs) are composed of reconfigurable ALU arrays and configuration cache (or context memory) to achieve high performance and flexibility. Specially, configuration cache is the main component in CGRA that provides distinct feature for dynamic reconfiguration in every cycle. However, frequent memory-read operations for dynamic reconfiguration cause much power consumption. Thus, reducing power in configuration cache has become critical for CGRA to be more competitive and reliable for its use in embedded systems. In this paper, we propose dynamically compressible context architecture for power saving in configuration cache. This power-efficient design of context architecture works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves up to 39.72% power in configuration cache with negligible area overhead (2.16%). 2009 IEEE.

authors

• Mahapatra, Rabinarayan

published proceedings

• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

author list (cited authors)

• Kim, Y., & Mahapatra, R. N.

citation count

• 40

complete list of authors

• Kim, Yoonjin||Mahapatra, Rabi N

publication date

• January 2010

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Very Large Scale Integration Systems  Journal

keywords

• Coarse-grained Reconfigurable Architecture (cgra)
• Configuration Cache
• Context Architecture
• Embedded System
• Low Power

Digital Object Identifier (DOI)

• 10.1109/TVLSI.2008.2006846

start page

• 15

end page

• 28

volume

• 18

issue

• 1

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftvlsi.2008.2006846