Clock Buffer Polarity Assignment for Power Noise Reduction Academic Article uri icon


  • Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively. 2009 IEEE.

published proceedings

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

author list (cited authors)

  • Samanta, R., Venkataraman, G., & Jiang Hu.

citation count

  • 8

complete list of authors

  • Samanta, R||Venkataraman, G

publication date

  • June 2009