A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain Academic Article uri icon


  • 2014 IEEE. A process-variation resilient current mode logic (CML) is presented. The proposed CML employs time-reference-based adaptive biasing chain with replica load to address performance degradation over the process variations. It adjusts variable load resistor to simultaneously regulate time constant, voltage swing, level shifting, and DC gain. The prototype demonstrates the process-variation resiliency of the proposed solution by showing performance degradation over the process corners. Over 20% of polygate resistance variation, the proposed CML suppresses the degradation of speed and rms jitter less than 4.3% and 0.15 ps while conventional CML results in 13% and 3.8-ps degradation, respectively.

published proceedings

  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

author list (cited authors)

  • Hyung-Joon Jeon, .., Silva-Martinez, J., & Hoyos, S.

citation count

  • 1

complete list of authors

  • Silva-Martinez, Jose||Hoyos, Sebastian

publication date

  • January 2015