Preliminary Models of the Cost of Fault Tolerance Conference Paper

abstract

• The use of Commercial Off-The-Shelf (COTS) microprocessors in safety-critical applications poses many challenges for system safety engineers. Due to liability and intellectual property concerns, important details, such as the Register Transfer Level (RTL) implementation of the microprocessor, are often unavailable to those qualifying systems for use in safety-critical applications. Therefore, engineers must rely on high level specifications and other documents in order to prove the safety of using these microprocessors. In this abstract, we describe a microprocessor safety analysis framework that may assist engineers facing this situation. This framework focuses on demonstrating the logical correctness of microprocessors by verifying their features. The five steps of this framework are Feature Identification, Feature Risks Analysis, Feature Modeling, Feature Verification, and Safety Analysis. 2007 IEEE.

name of conference

• 10th IEEE High Assurance Systems Engineering Symposium (HASE'07)

authors

• Mahapatra, Rabinarayan

published proceedings

• 10th IEEE High Assurance Systems Engineering Symposium (HASE'07)

author list (cited authors)

• Leach, R. J.

citation count

• 0

complete list of authors

• Leach, Ronald J

publication date

• November 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings / IEEE International Symposium on High-Assurance Systems Engineering. IEEE International Symposium on High-Assurance Systems Engineering  Journal

Digital Object Identifier (DOI)

• 10.1109/hase.2007.11

International Standard Book Number (ISBN) 10

• 0769530435

International Standard Book Number (ISBN) 13

• 9780769530437

start page

• 371

end page

• 372

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fhase.2007.11