Performance driven global routing through gradual refinement Academic Article uri icon


  • We propose a heuristic for VLSI interconnect global routing that can optimize routing congestion, delay and number of bends, which are often competing objectives. Routing flexibilities under timing constraints are obtained and exploited to reduce congestion subject to timing constraints. The wire routes are determined through gradual refinement according to probabilistic estimation on congestions so that the congestion is minimized while the number of bends on wires is limited. The experiments on both random generated circuits and benchmark circuits confirm the effectiveness of this method.

published proceedings


author list (cited authors)

  • Hu, J., & Sapatnekar, S. S.

citation count

  • 2

complete list of authors

  • Hu, J||Sapatnekar, SS

publication date

  • January 2002