Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders Conference Paper uri icon


  • This paper concerns the variation tolerance in signal processing integrated circuits. Motivated by the fact that variation-induced timing faults at different locations in signal processing circuits have different effects on the signal processing performance, we developed an importance-aware clock skew scheduling technique, called soft clock skew scheduling, that can realize system-level tolerance to variation-induced timing faults. With state-parallel Viterbi decoders as test vehicles, we demonstrated its effectiveness on increasing the achievable clock frequency in presence of significant variation-induced timing faults, while maintaining good decoding performance. 2007 IEEE.

name of conference

  • 8th International Symposium on Quality Electronic Design (ISQED'07)

published proceedings

  • 8th International Symposium on Quality Electronic Design (ISQED'07)

author list (cited authors)

  • Liu, Y., Zhang, T., & Hu, J.

citation count

  • 0

complete list of authors

  • Liu, Yang||Zhang, Tong||Hu, Jiang

publication date

  • March 2007