Soft clock skew scheduling for variation-tolerant signal processing circuits: A case study of viterbi decoders Conference Paper

abstract

• This paper concerns the variation tolerance in signal processing integrated circuits. Motivated by the fact that variation-induced timing faults at different locations in signal processing circuits have different effects on the signal processing performance, we developed an importance-aware clock skew scheduling technique, called soft clock skew scheduling, that can realize system-level tolerance to variation-induced timing faults. With state-parallel Viterbi decoders as test vehicles, we demonstrated its effectiveness on increasing the achievable clock frequency in presence of significant variation-induced timing faults, while maintaining good decoding performance. 2007 IEEE.

name of conference

• 8th International Symposium on Quality Electronic Design (ISQED'07)

authors

• Hu, Jiang

published proceedings

• ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN

author list (cited authors)

• Liu, Y., Zhang, T., & Hu, J.

citation count

• 0

complete list of authors

• Liu, Yang||Zhang, Tong||Hu, Jiang

publication date

• March 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/isqed.2007.146

International Standard Book Number (ISBN) 10

• 0769527957

International Standard Book Number (ISBN) 13

• 978-0-7695-2795-6

start page

• 749

end page

• +

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fisqed.2007.146