In the advent of smaller devices, a significant increase in the density of on-chip components has raised congestion and overflow as critical issues in VLSI physical design automation. In this paper, we present novel techniques for reducing congestion and minimizing overflows. Our methods are based on ripping up nets that go through the congested areas and replacing them with
congestion-awaretopologies. Our contributions can be summarized as follows. First, we present several efficient algorithms for finding congestion-awareSteiner trees that is, trees that avoid congested areas of the chip. Next, we show that the novel technique of network codingcan lead to further improvements in routability, reduction of congestion, and overflow avoidance. Finally, we present an algorithm for identifying efficient congestion-aware network coding topologies. We evaluate the performance of the proposed algorithms through extensive simulations.