High performance clock routing in X-architecture
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As a promising approach to mitigate the challenge of interconnect limit, X-architecture allows routings along diagonal directions in addition to rectilinear directions. It can reduce routing wirelength and vias number compared with conventional Manhattan routing. Although Steiner minimum tree and signal routing algorithms have been developed for X-architecture, clock routing has not been addressed to the best of our knowledge. However, wirelength reduction is even more compelling for clock net, as wire is a major power consumer and power supply noise generator. In addition, X-architecture is very effective for interconnect delay and clock skew optimization. In this paper, we investigate the layout embedding technique for clock routing in X-architecture and integrate it with the Deferred-Merge Embedding (DME) algorithm. To alleviate the inaccuracy of the Elmore delay (ED) model, a more accurate Fitted Elmore delay (FED) model is employed. Experimental results on benchmarks exhibit encouraging results. ©2006 IEEE.
author list (cited authors)
Shen, W., Cai, Y., Hu, J., Hong, X., Lu, B., & IEEE, ..