Case Studies on Variation Tolerant and Low Power Design using Planar Asymmetric Double Gate Transistor Conference Paper uri icon

abstract

  • © 2014 IEEE. In nanometer technologies, low power and process variation control have emerged as the first order design goal after high performance. Short channel effects (SCEs) deteriorate the MOSFET performance and lead to higher leakage power. Process variations cause high variability in power consumption and performance of an IC which affects the overall yield. Double gate devices suppress SCEs and are potential candidates for replacing Bulk technology in nanometer nodes. Threshold voltage control in planar asymmetric double gate transistor (IGFET) using a fourth terminal provides an effective means of combating process variations and low power design. In this paper, we analyze the suitability of IGFET for variation control and low power design. We present extensive comparison between IGFET and Bulk for reducing variability, improving yield and leakage power reduction using threshold voltage modulation. BSIM-IMG models were used for IGFET based simulations. Experimental results show that IGFET is highly suitable for adaptive applications and performs better than Bulk while substantially reducing leakage power.

author list (cited authors)

  • Singh, A., & Hu, J.

citation count

  • 0

publication date

  • August 2014

publisher