VLSI technology scaling has caused interconnect delay to increasingly dominate the overall chip performance. Optimization techniques such as buffer insertion, wire sizing and layer assignment play critical roles in successful timing closure for chip designs. For several VLSI technology generations, designers have confronted the challenges associated with increasing wire delays. One industrial solution is to add layers of thicker metal to the wiring stacks. However, the existing physical synthesis tools are not effective enough to handle these new thick metal layers. Thus, it is necessary to design a new flow to provide better communication among layer planning, buffering, routing and different optimization engines. In this thesis, our work proposes a new design flow, Layer Centric Design Flow, to perform congestion mitigation and timing optimization with layer directives. Our design flow balances buffer and routing resources so that the design benefits from the availability of thick metal layers and reduces buffer usage while maintaining routability as well as performance.
