A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment Conference Paper uri icon


  • Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on discretizing continuous optimization solutions. Sensitivity-driven heuristics are easily trapped in local optima and the discretization may be subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and Vt assignment. The core idea of this approach is joint relaxation and restriction, which employs consistency relaxation and coupled bi-directional solution search. The process of joint relaxation and restriction is conducted iteratively to systematically improve solutions. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. The results from our algorithm can lead to about 22% less power dissipation subject to the same timing constraints. 2010 IEEE.

published proceedings

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

altmetric score

  • 3

author list (cited authors)

  • Liu, Y., & Hu, J.

citation count

  • 52

complete list of authors

  • Liu, Yifang||Hu, Jiang

publication date

  • February 2010