Register placement for low power clock network Conference Paper uri icon


  • In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results. 2005 IEEE.

published proceedings

  • Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

author list (cited authors)

  • Lu, Y., Sze, C. N., Hong, X., Zhou, Q., Cai, Y., Huang, L., & Hu, J.

complete list of authors

  • Lu, Y||Sze, CN||Hong, X||Zhou, Q||Cai, Y||Huang, L||Hu, J

publication date

  • December 2005