A practical methodology for early buffer and wire resource allocation
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As technology scales, interconnect-centric design flows become imperative for achieving timing closure. Preplanning buffers and wires in the layout is critical for such flows. Both buffers and wires must be considered simultaneously, since wire routes determine buffer requirements and buffer locations constrain the wire routes. In contrast to recently proposed buffer-block planning approaches, our novel design methodology distributes a set of buffer sites throughout the design. This allows one to use a tile graph to abstract the buffer planning problem and simultaneously address wire planning. We present a four-stage heuristic called resource allocation for buffer and interconnect distribution for resource allocation that includes a new, efficient technique for buffer insertion using a length-based constraint. Extensive experiments validate the effectiveness of this approach.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
author list (cited authors)
Alpert, C. J., Jiang Hu, .., Sapatnekar, S. S., & Villarrubia, P. G.
complete list of authors
Alpert, CJ||Sapatnekar, SS||Villarrubia, PG