A new algorithm for simultaneous gate sizing and threshold voltage assignment Conference Paper uri icon


  • Gate sizing and threshold voltage (Vt) assignment are popular techniques for circuit timing and power optimization. Existing methods, by and large, are either sensitivity-driven heuristics or based on rounding continuous optimization solutions. Sensitivity-driven heuristics are easily trapped in local optimum and the rounding is subject to remarkable errors. In this paper, we propose a systematic combinatorial approach for simultaneous gate sizing and Vt assignment. The core ideas of this approach include consistency relaxation and coupled bi-directional search. Our algorithm is compared with a state-of-the-art previous work on benchmark circuits. The results from our algorithm can lead to about 24% less power dissipation subject to the same timing constraints. Copyright 2009 ACM.

name of conference

  • the 2009 international symposium

published proceedings

  • Proceedings of the 2009 international symposium on Physical design - ISPD '09

author list (cited authors)

  • Liu, Y., & Hu, J.

citation count

  • 18

complete list of authors

  • Liu, Yifang||Hu, Jiang

publication date

  • January 2009