Built-In Proactive Tuning System for Circuit Aging Resilience Conference Paper uri icon

abstract

  • VLSI circuits in nanometer VLSI technology experience significant aging effects, which are embodied by performance degradation over operation time. Although this degradation can be compensated by over-design, it induces remarkable power overhead which is undesirable in tightly power-constrained designs. Dynamic voltage scaling (DVS) is a more power-efficient approach. However, its coarse granularity implies difficulty in handling fine-grained variations in the aging effects. We propose a Built-In Proactive Tuning (BIPT) system that allows each circuit block to autonomously tune its performance according to its own degree of aging. The BIPT system is validated through SPICE simulations on benchmark circuits with consideration of NBTI effect. The experimental results indicate that the proposed BIPT system leads to about 45% less power than the approach of over-design while maintaining the same performance. Compared to DVS, BIPT can achieve the same aging resilience with about 30% less power dissipation. 2008 IEEE.

name of conference

  • 2008 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTVS)

published proceedings

  • 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

author list (cited authors)

  • Shah, N., Samanta, R., Zhang, M., Hu, J., & Walker, D.

citation count

  • 13

complete list of authors

  • Shah, Nimay||Samanta, Rupak||Zhang, Ming||Hu, Jiang||Walker, Duncan

publication date

  • October 2008

publisher