publication venue for
- Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits 2020
- Impact of Test Compression on Power Supply Noise Control 2015
- Mixed Structural-Functional Path Delay Test Generation and Compaction 2013
- Shielding Heterogeneous MPSoCs from Untrustworthy 3PIPs through Security-Driven Task Scheduling 2013
- A Low Overhead Built-In Delay Testing with Voltage and Frequency Adaptation for Variation Resilience 2012
- Challenges in Delay Testing of Integrated Circuits 2009
- Built-In Proactive Tuning System for Circuit Aging Resilience 2008
- Adaptive Design for Performance-Optimized Robustness**This work was supported in part by the IBM Faculty Partnership Award Program, and in part by the Gigascale Systems Research Center at UC Berkeley under contract 2003-DT-660 from Microelectronics Advanced Research Corporation (MARCO). 2006
- Timing Failure Analysis of Commercial CPUs Under Operating Stress 2006
- A fast algorithm for critical path tracing in VLSI digital circuits 2005
- CROWNE: Current Ratio outliers with neighbor estimator 2003
- CROWNE: Current ratio outliers with neighbor estimator 2003
- Chip level power supply partitioning for I-DDQ testing using built-in current sensors 2003
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Chip level power supply partitioning for I
DDQ testing using built-in current sensors 2003 - CodSim - A combined delay fault simulator 2003
- CodSim - A combined delay fault simulator 2003
- Neighbor current ratio (NCR): A new metric for I-DDQ data analysis 2002
- Accurate fault modeling and fault simulation of resistive bridges 1998
- Tolerance of delay faults 1992
- Circuit-level modeling of spot defects 1991